Datasheet

Datasheet, Volume 2 279
Processor Uncore Configuration Registers
4.1.4 PCISTS—PCI Status Register
PCISTS
Offset: 6h
Bit Attr
Reset
Value
Description
15 RO 0b
Detected Parity Error
This bit is set when the device receives a packet on the primary side with an
uncorrectable data error (including a packet with poison bit set) or an
uncorrectable address/control parity error. The setting of this bit is regardless of
the Parity Error Response bit (PERRE) in the PCICMD register. R2PCIe will never
set this bit.
14 RO 0b
Signaled System Error
Hardwired to 0
13 RO 0b
Received Master Abort
Hardwired to 0
12 RO 0b
Received Target Abort
Hardwired to 0
11 RO 0b
Signaled Target Abort
Hardwired to 0
10:9 RO 0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
8RO 0b
Master Data Parity Error
Hardwired to 0
7RO 0b
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
6RO 0bReserved
5RO 0b
66MHz capable
Not applicable to PCI Express. Hardwired to 0.
4RO 0b
Capabilities List
This bit indicates the presence of a capabilities list structure
3RO 0b
INTx Status
Hardwired to 0
2:0 RV 0h Reserved