Datasheet

Processor Uncore Configuration Registers
278 Datasheet, Volume 2
4.1.3 PCICMD—PCI Command Register
PCICMD
Offset: 4h
Bit Attr
Reset
Value
Description
15:11 RV 0h Reserved
10 RO 0b
INTx Disable
Not applicable for these devices
9RO0b
Fast Back-to-Back Enable
Not applicable to PCI Express and is hardwired to 0
8RO0b
SERR Enable
This bit has no impact on error reporting from these devices
7RO0b
IDSEL Stepping/Wait Cycle Control
Not applicable to internal devices. Hardwired to 0.
6RO0b
Parity Error Response
This bit has no impact on error reporting from these devices
5RO0b
VGA palette snoop Enable
Not applicable to internal devices. Hardwired to 0.
4RO0b
Memory Write and Invalidate Enable
Not applicable to internal devices. Hardwired to 0.
3RO0b
Special Cycle Enable
Not applicable. Hardwired to 0.
2RO0b
Bus Master Enable
Hardwired to 0 since these devices do not generate any transactions
1RO0b
Memory Space Enable
Hardwired to 0 since these devices do not decode any memory BARs
0RO0b
IO Space Enable
Hardwired to 0 since these devices do not decode any IO BARs