Datasheet

Processor Integrated I/O (IIO) Configuration Registers
274 Datasheet, Volume 2
3.3.8.65 VTD1_INV_COMP_EVT_ADDR—Invalidation Completion 
Event Address Register
3.3.8.66 VTD1_INTR_REMAP_TABLE_BASE—Interrupt Remapping Table 
Base Address Register
3.3.8.67 VTD1_FLTREC0_GPA—Fault Record Register
15:0 RW 0h Interrupt Data
VTD1_INV_COMP_EVT_ADDR
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 10A8h
Bit Attr
Reset
Value
Description
63:2 RW 0h Interrupt Address
1:0 RV 0h Reserved
VTD1_INTR_REMAP_TABLE_BASE
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 10B8h
Bit Attr
Reset
Value
Description
63:12 RW 0h
Intr Remap Base
This field points to the base of page-aligned interrupt remapping table. If the
Interrupt Remapping Table is larger than 4 KB in size, it must be size-aligned.
Reads of this field returns value that was last programmed to it.
11 RW-LB 0b
IA-32 Extended Interrupt Enable
0 = IA-32 system is operating in legacy IA32 interrupt mode. Hardware interprets
only 8-bit APICID in the Interrupt Remapping Table entries.
1 = IA-32 system is operating in extended IA-32 interrupt mode. Hardware
interprets 32-bit APICID in the Interrupt Remapping Table entries.
10:4 RV 0h Reserved
3:0 RW 0b
Size
This field specifies the size of the interrupt remapping table. The number of
entries in the interrupt remapping table is 2^(X+1), where X is the value
programmed in this field.
VTD1_FLTREC0_GPA
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 1100h
Bit Attr
Reset
Value
Description
63:12 ROS-V 0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0 RV 0h Reserved
VTD1_INV_COMP_EVT_DATA
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 10A4h
Bit Attr
Reset
Value
Description