Datasheet

Processor Integrated I/O (IIO) Configuration Registers
272 Datasheet, Volume 2
3.3.8.59 VTD1_INV_QUEUE_HEAD—Invalidation Queue Header 
Pointer Register
3.3.8.60 VTD1_INV_QUEUE_TAIL—Invalidation Queue Tail 
Pointer Register
3.3.8.61 VTD1_INV_QUEUE_ADD—Invalidation Queue 
Address Register
VTD1_INV_QUEUE_HEAD
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 1080h
Bit Attr
Reset
Value
Description
63:19 RV 0h Reserved
18:4 RO-V 0000h
Queue Head
This field specifies the offset (128-bit aligned) to the invalidation queue for the
command that will be fetched next by hardware. This field is incremented after the
command has been fetched successfully and has been verified to be a valid/
supported command.
3:0 RV 0h Reserved
VTD1_INV_QUEUE_TAIL
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 1088h
Bit Attr
Reset
Value
Description
63:19 RV 0h Reserved
18:4 RW 0h
Queue Tail
This field specifies the offset (128-bit aligned) to the invalidation queue for the
command that will be written next by software.
3:0 RV 0h Reserved
VTD1_INV_QUEUE_ADD
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 1090h
Bit Attr
Reset
Value
Description
63:12 RW
000000
000000
0h
Invalidation Request Queue Base Address
This field points to the base of size-aligned invalidation request queue.
11:3 RV 0h Reserved
2:0 RW 0h
Queue Size
This field specifies the length of the invalidation request queue. The number of
entries in the invalidation queue is defined as 2^(X + 8) , where X is the value
programmed in this field.