Datasheet

Datasheet, Volume 2 269
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Processor Integrated I/O (IIO) Configuration Registers
3.3.8.51 VTD1_FLTEVTCTRL—Fault Event Control Register
3.3.8.52 VTD1_FLTEVTDATA—Fault Event Data Register
VTD1_FLTEVTCTRL
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 1038h
Bit Attr
Reset
Value
Description
31 RW 1b
Interrupt Message Mask
0 = Hardware is prohibited from issuing interrupt message requests.
1 = Software has cleared this bit to indicate interrupt service is available. When a
faulting condition is detected, hardware may issue a interrupt request (using
the fault event data and fault event address register values) depending on
the state of the interrupt mask and interrupt pending bits.
30 RO 0b
Interrupt Pending
Hardware sets the IP field whenever it detects an interrupt condition. Interrupt
condition is defined as when an interrupt condition occurs when hardware records
a fault through one of the Fault Recording registers and sets the PPF field in Fault
Status register. - Hardware detected error associated with the Invalidation Queue,
setting the IQE field in the Fault Status register.
• Hardware detected invalidation completion timeout error, setting the ICT field
in the Fault Status register.
• If any of the above status fields in the Fault Status register was already set at
the time of setting any of these fields, it is not treated as a new interrupt
condition.
The IP field is kept set by hardware while the interrupt message is held pending.
The interrupt message could be held pending due to interrupt mask (IM field)
being set, or due to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced. This could be due to either
• Hardware issuing the interrupt message due to either change in the transient
hardware condition that caused interrupt message to be held pending or due
to software clearing the IM field.
• Software servicing all the pending interrupt status fields in the Fault Status
register.
— PPF field is cleared by hardware when it detects all the Fault Recording
registers have Fault (F) field clear.
— Other status fields in the Fault Status register is cleared by software
writing back the value read from the respective fields.
29:0 RV 0h Reserved
VTD1_FLTEVTDATA
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 103Ch
Bit Attr
Reset
Value
Description
31:16 RV 0h Reserved
15:0 RW 0h Interrupt Data