Datasheet

Processor Integrated I/O (IIO) Configuration Registers
266 Datasheet, Volume 2
3.3.8.47 VTD1_GLBSTS—Global Status Register
3.3.8.48 VTD1_ROOTENTRYADD—Root Entry Table Address Register
VTD1_GLBSTS
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 101Ch
Bit Attr
Reset
Value
Description
31 RO 0b
Translation Enable Status
When set, indicates that translation hardware is enabled and when clear indicates
the translation hardware is not enabled.
30 RO 0b
Set Root Table Pointer Status
This field indicates the status of the root- table pointer in hardware.This field is
cleared by hardware when software sets the SRTP field in the Global Command
register. This field is set by hardware when hardware finishes the set root-table
pointer operation (by performing an implicit global invalidation of the context-
cache and IOTLB, and setting/updating the root-table pointer in hardware with the
value provided in the Root-Entry Table Address register).
29 RO 0b
Set Fault Log Pointer Status
Not applicable to the processor
28 RO 0b
Advanced Fault Logging Status
Not applicable to the processor
27 RO 0b
Write Buffer Flush Status
Not applicable to the processor
26 RO 0b
Queued Invalidation Interface Status
IIO sets this bit once it has completed the software command to enable the
queued invalidation interface. Till then this bit is 0.
25 RO 0b
Interrupt Remapping Enable Status
OH sets this bit once it has completed the software command to enable the
interrupt remapping interface. Till then this bit is 0.
24 RO 0b
Interrupt Remapping Table Pointer Status
This field indicates the status of the interrupt remapping table pointer in
hardware. This field is cleared by hardware when software sets the SIRTP field in
the Global Command register. This field is set by hardware when hardware
completes the set interrupt remap table pointer operation using the value
provided in the Interrupt Remapping Table Address register.
23 RO 0b
Compatibility Format Interrupt Status
The value reported in this field is applicable only when interrupt-remapping is
enabled and Legacy interrupt mode is active.
0 = Compatibility format interrupts are blocked.
1 = Compatibility format interrupts are processed as pass-through (bypassing
interrupt remapping).
22:0 RV 0h Reserved
VTD1_ROOTENTRYADD
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 1020h
Bit Attr
Reset
Value
Description
63:12 RW 0h
Root Entry Table Base Address
4K aligned base address for the root entry table. The processor does not use bits
63:43 and checks for them to be 0. Software specifies the base address of the
root-entry table through this register, and enables it in hardware through the
SRTP field in the Global Command register. Reads of this register returns value
that was last programmed to it.
11:0 RV 0h Reserved