Datasheet

Datasheet, Volume 2 263
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Processor Integrated I/O (IIO) Configuration Registers
3.3.8.45 VTD1_EXT_CAP—Extended Intel
®
VT-d Capability Register
6RO 1b
PHMR Support
Processor supports protected high memory range
5RO 1b
PLMR Support
Processor supports protected low memory range
4RO 0b
RWBF
Not applicable for the processor
3RO 0b
Advanced Fault Logging
Processor does not support advanced fault logging
2:0 RO 010b
Number of Domains Supported
Processor supports 256 domains with 8 bit domain ID
VTD1_EXT_CAP
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 1010h
Bit Attr
Reset
Value
Description
63:24 RV 0h Reserved
23:20 RO Fh
Maximum Handle Mask Value
IIO supports all 16 bits of handle being masked. Note IIO always performs global
interrupt entry invalidation on any interrupt cache invalidation command and
hardware never really looks at the mask value.
19:18 RV 0h Reserved
17:8 RO 20h
Invalidation Unit Offset
IIO has the invalidation registers at offset 200h
7RWO 0b
Snoop Control
0 = Hardware does not support 1-setting of the SNP field in the page-table
entries.
1 = Hardware supports the 1-setting of the SNP field in the page-table entries.
IIO supports snoop override only for the non-isoch Intel VT-d engine
6RW-O 1b
Pass through
IIO supports pass through. This bit is RW-O for defeaturing in case of post-si
bugs.
5RO 1b
Caching Hints
IIO supports caching hints
4RO 1b
IA32 Extended Interrupt Mode
IIO supports the extended interrupt mode
3RWO 1b
Interrupt Remapping Support
IIO supports this
2RO 0b
Device TLB support
IIO supports ATS for the non-isoch Intel VT-d engine. This bit is RW-O for non-
isoch engine in case we might have to defeature ATS post-si.
1RWO 1b
Queued Invalidation support
IIO supports this
0RW-O 0b
Coherency Support
BIOS can write to this bit to indicate to hardware to either snoop or not-snoop the
DMA/Interrupt table structures in memory (root/context/pd/pt/irt). This bit is
expected to be always set to 0 for the Intel High Definition Audio Intel VT-d engine
and programmability is only provided for that engine for debug reasons.
VTD1_CAP
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 1008h
Bit Attr
Reset
Value
Description