Datasheet

Introduction
26 Datasheet, Volume 2
Execute Disable Bit
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel
®
64 and IA-32 Architectures Software
Developer's Manuals for more detailed information.
Functional Operation
Refers to the normal operating conditions in which all processor specifications,
including DC, AC, system bus, signal quality, mechanical, and thermal, are
satisfied.
Home Agent (HA)
Responsible for memory transaction through the Ring and handles incoming/
outgoing memory transactions
Integrated Heat Spreader
(IHS)
A component of the processor package used to enhance the thermal
performance of the package. Component thermal solutions interface with the
processor at the IHS surface.
Integrated Memory
Controller (IMC)
The Memory Controller is integrated on the processor die.
Intel
®
64 Technology 64-bit memory extensions to the IA-32 architecture.
Intel
®
Turbo Boost
Technology
Intel
®
Turbo Boost Technology is a way to automatically run the processor core
faster than the marked frequency if the part is operating under power, temper-
ature, and current specifications limits of the Thermal Design Power (TDP). This
results in increased performance of both single and multi-threaded applications.
Intel
®
Virtualization
Technology (Intel
®
VT)
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
Intel
®
VT-d
Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O. Intel VT-d is a
hardware assist, under system software (Virtual Machine Manager or OS)
control, for enabling I/O device virtualization. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA remapping, a
key feature of Intel VT-d.
IOV I/O Virtualization
Jitter
Any timing variation of a transition edge or edges from the defined Unit Interval
(UI).
LGA2011 Socket
The 2011-land FC-LGA package mates with the system board through this
surface mount, 2011-contact socket.
NCTF
Non-Critical to Function: NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
NTB Non-Transparent Bridge
PCH
Platform Controller Hub. The next generation chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PCU Power Control Unit.
PECI Platform Environment Control Interface
Processor The 64-bit, single-core or multi-core component (package)
Processor Core
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
Rank
A unit of DRAM corresponding four to eight devices in parallel. These devices are
usually, but not always, mounted on a single side of a DDR3 DIMM.
Ring Processor interconnect between the different Uncore modules
RP Indicate Root Port for PCI Express
SCI System Control Interrupt. Used in ACPI protocol.
Table 1-1. Processor Terminology (Sheet 2 of 3)
Term Description