Datasheet

Datasheet, Volume 2 253

Processor Integrated I/O (IIO) Configuration Registers
3.3.8.25 VTD0_FLTREC0_GPA—Fault Record Register
3.3.8.26 VTD0_FLTREC0_SRC—Fault Record Register
3.3.8.27 VTD0_FLTREC1_GPA—Fault Record Register
VTD0_FLTREC0_GPA
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 100h
Bit Attr
Reset
Value
Description
63:12 ROS-V 0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0 RV 0h Reserved
VTD0_FLTREC0_SRC
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 108h
Bit Attr
Reset
Value
Description
63 RW1CS 0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
62 ROS-V 0b
Type
Type of the first faulted DMA request
0 = DMA write
1 = DMA read request
This field is only valid when Fault (F) bit is set.
61:60 ROS-V 00b
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
59:40 RV 0h Reserved
39:32 ROS-V 00h
Fault Reason
This field provies the Reason for the first translation fault. See Intel VT-d
specification for details. This field is only valid when Fault bit is set.
31:16 RV 0h Reserved
15:0 ROS-V 0000h
Source Identifier
Requester ID of the DMA request that faulted. Valid only when F bit is set
VTD0_FLTREC1_GPA
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 110h
Bit Attr
Reset
Value
Description
63:12 ROS-V 0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0 RV 0h Reserved