Datasheet

Processor Integrated I/O (IIO) Configuration Registers
252 Datasheet, Volume 2
3.3.8.22 VTD0_INV_COMP_EVT_DATA—Invalidation Completion Event 
Data Register
3.3.8.23 VTD0_INV_COMP_EVT_ADDR—Invalidation Completion 
Event Address Register
3.3.8.24 VTD0_INTR_REMAP_TABLE_BASE—Interrupt Remapping Table 
Base Address Register
VTD0_INV_COMP_EVT_DATA
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: A4h
Bit Attr
Reset
Value
Description
31:16 RV 0h Reserved
15:0 RW 0h Interrupt Data
VTD0_INV_COMP_EVT_ADDR
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: A8h
Bit Attr
Reset
Value
Description
63:2 RW 0h Interrupt Address
1:0 RV 0h Reserved
VTD0_INTR_REMAP_TABLE_BASE
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: B8h
Bit Attr
Reset
Value
Description
63:12 RW 0h
Intr Remap Base
This field points to the base of page-aligned interrupt remapping table. If the
Interrupt Remapping Table is larger than 4 KB in size, it must be size-aligned.
Reads of this field return the value that was last programmed to it.
11 RW-LB 0b
IA32 Extended Interrupt Enable
0 = IA32 system is operating in legacy IA32 interrupt mode. Hardware interprets
only 8-bit APICID in the Interrupt Remapping Table entries.
1 = IA32 system is operating in extended IA32 interrupt mode. Hardware
interprets 32-bit APICID in the Interrupt Remapping Table entries.
10:4 RV 0h Reserved
3:0 RW 0b
Size
This field specifies the size of the interrupt remapping table. The number of
entries in the interrupt remapping table is 2^(X+1), where X is the value
programmed in this field.