Datasheet
Datasheet, Volume 2 249
Processor Integrated I/O (IIO) Configuration Registers
3.3.8.14 VTD0_PROT_LOW_MEM_LIMIT—Protected Memory Low
Limit Register
3.3.8.15 VTD0_PROT_HIGH_MEM_BASE—Protected Memory High
Base Register
3.3.8.16 VTD0_PROT_HIGH_MEM_LIMIT—Protected Memory High
Limit Register
VTD0_PROT_LOW_MEM_LIMIT
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 6Ch
Bit Attr
Reset
Value
Description
31:21 RW-LB 000h
Low protected DRAM region
16 MB aligned limit address of the low protected DRAM region
Intel VT-d engine generated reads/writes (page walk, interrupt queue, invalidation
queue read, invalidation status) are allowed toward this region; but no DMA
accesses (non-translated DMA or ATS translated DMA or pass through DMA; that
is, no DMA access of any kind) from any device is allowed toward this region
(regardless of whether TE is 0 or 1), when enabled.
20:0 RV 0h Reserved
VTD0_PROT_HIGH_MEM_BASE
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 70h
Bit Attr
Reset
Value
Description
63:21 RW-LB
000000
00000h
High protected DRAM region
16 MB aligned base address of the high protected DRAM region
Intel VT-d engine generated reads/writes (page walk, interrupt queue, invalidation
queue read, invalidation status) are allowed toward this region; but no DMA
accesses (non-translated DMA or ATS translated DMA or pass through DMA; that
is, no DMA access of any kind) from any device is allowed toward this region
(regardless of whether TE is 0 or 1), when enabled.
20:0 RV 0h Reserved
VTD0_PROT_HIGH_MEM_LIMIT
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 78h
Bit Attr
Reset
Value
Description
63:21 RW-LB
000000
00000h
High protected DRAM region
16 MB aligned limit address of the high protected DRAM region
Intel VT-d engine generated reads/writes (page walk, interrupt queue, invalidation
queue read, invalidation status) are allowed toward this region; but no DMA
accesses (non-translated DMA or ATS translated DMA or pass through DMA; that
is, no DMA access of any kind) from any device is allowed toward this region
(regardless of whether TE is 0 or 1), when enabled.
20:0 RV 0h Reserved