Datasheet

Processor Integrated I/O (IIO) Configuration Registers
248 Datasheet, Volume 2
3.3.8.11 VTD0_FLTEVTADDR—Fault Event Address Register
3.3.8.12 VTD0_PMEN—Protected Memory Enable Register
3.3.8.13 VTD0_PROT_LOW_MEM_BASE—Protected Memory Low 
Base Register
VTD0_FLTEVTADDR
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 40h
Bit Attr
Reset
Value
Description
63:2 RW
000000
000000
0000h
Interrupt Address
The interrupt address is interpreted as the address of any other interrupt from a
PCI Express port.
1:0 RV 0h Reserved
VTD0_PMEN
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 64h
Bit Attr
Reset
Value
Description
31 RW-LB 0b
Enable Protected Memory
Enable Protected Memory PROT_LOW_BASE/LIMIT and PROT_HIGH_BASE/LIMIT
memory regions.
Software can use the protected low/high address ranges to protect both the DMA
remapping tables and the interrupt remapping tables. There is no separate set of
registers provided for each.
30:1 RV 0h Reserved
0RO0b
Protected Region Status
This bit is set by the processor when it has completed enabling the protected
memory region per the rules stated in the Intel VT-d specification.
VTD0_PROT_LOW_MEM_BASE
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 68h
Bit Attr
Reset
Value
Description
31:21 RW-LB 000h
Low protected DRAM region base
16 MB aligned base address of the low protected DRAM region
Intel VT-d engine generated reads/writes (page walk, interrupt queue, invalidation
queue read, invalidation status) are allowed toward this region; but no DMA
accesses (non-translated DMA or ATS translated DMA or pass through DMA; that
is, no DMA access of any kind) from any device is allowed toward this region
(regardless of whether TE is 0 or 1), when enabled.
20:0 RV 0h Reserved