Datasheet

Processor Integrated I/O (IIO) Configuration Registers
244 Datasheet, Volume 2
3.3.8.6 VTD0_ROOTENTRYADD—Root Entry Table Address Register
3.3.8.7 VTD0_CTXCMD—Context Command Register
22:0 RV 0h Reserved
VTD0_ROOTENTRYADD
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 20h
Bit Attr
Reset
Value
Description
63:12 RW 0h
Root Entry Table Base Address
4K aligned base address for the root entry table. The processor does not use bits
63:43 and checks for them to be 0. Software specifies the base address of the
root-entry table through this register, and enables it in hardware through the
SRTP field in the Global Command register. Reads of this register returns a value
that was last programmed to it.
11:0 RV 0h Reserved
VTD0_CTXCMD
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 28h
Bit Attr
Reset
Value
Description
63 RW 0b
Invalidate Context Entry Cache
Software requests invalidation of context-cache by setting this field. Software
must also set the requested invalidation granularity by programming the CIRG
field. Software must read back and check the ICC field to be clear to confirm the
invalidation is complete. Software must not update this register when this field is
set. Hardware clears the ICC field to indicate the invalidation request is complete.
Hardware also indicates the granularity at which the invalidation operation was
performed through the CAIG field. Software must not submit another invalidation
request through this register while the ICC field is set.Software must submit a
context cache invalidation request through this field only when there are no
invalidation requests pending at this DMA-remapping hardware unit. Since
information from the context-cache may be used by hardware to tag IOTLB
entries, software must perform domain-selective (or global) invalidation of IOTLB
after the context cache invalidation has completed.
VTD0_GLBSTS
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 1Ch
Bit Attr
Reset
Value
Description