Datasheet

Processor Integrated I/O (IIO) Configuration Registers
242 Datasheet, Volume 2
27 RO 0b
Write Buffer Flush
Not Applicable to the processor
26 RW 0b
Queued Invalidation Enable
Software writes to this field to enable queued invalidations.
0 = Disable queued invalidations. In this case, invalidations must be performed
through the Context Command and IOTLB Invalidation Unit registers.
1 = Enable use of queued invalidations. Once enabled, all invalidations must be
submitted through the invalidation queue and the invalidation registers
cannot be used till the translation has been disabled. The invalidation queue
address register must be initialized before enabling queued invalidations.
Also software must make sure that all invalidations submitted prior using the
register interface are all completed before enabling the queued invalidation
interface.
Hardware reports the status of queued invalidation enable operation through QIES
field in the Global Status register. Value returned on read of this field is undefined.
25 RW 0b
Interrupt Remapping Enable
0 = Disable Interrupt Remapping Hardware
1 = Enable Interrupt Remapping Hardware
Hardware reports the status of the interrupt-remap enable operation through the
IRES field in the Global Status register.
Before enabling (or re-enabling) Interrupt-remapping hardware through this field,
software must:
• Setup the interrupt-remapping structures in memory
• Set the Interrupt Remap table pointer in hardware (through IRTP field).
• Perform global invalidation of IOTLB
There may be active interrupt requests in the platform when software updates this
field. Hardware must enable or disable remapping logic only at deterministic
transaction boundaries, so that any in-flight interrupts are either subject to
remapping or not at all. IIO must drain any in-flight translated DMA read/write,
MSI interrupt requests queued within the root complex before completing the
translation enable command and reflecting the status of the command through
the IRES field in the GSTS_REG. Value returned on read of this field is undefined.
24 RW 0b
Set Interrupt Remap Table Pointer
Software sets this field to set/update the interrupt remapping table pointer used
by hardware. The interrupt remapping table pointer is specified through the
Interrupt Remapping Table Address register.Hardware reports the status of the
interrupt remapping table pointer set operation through the IRTPS field in the
Global Status register.
The interrupt remap table pointer set operation must be performed before
enabling or re-enabling (after disabling) interrupt remapping hardware through
the IRE field.
After an interrupt remap table pointer set operation, software must globally
invalidate the interrupt entry cache. This is required to ensure hardware uses only
the interrupt remapping entries referenced by the new interrupt remap table
pointer, and not any stale cached entries.
While interrupt remapping is active, software may update the interrupt remapping
table pointer through this field. However, to ensure valid in-flight interrupt
requests are deterministically remapped, software must ensure that the
structures referenced by the new interrupt remap table pointer are programmed
to provide the same remapping results as the structures referenced by the
previous interrupt remap table pointer. Clearing this bit has no effect. IIO
hardware internally clears this field before the ’set’ operation requested by
software has take effect.
VTD0_GLBCMD
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 18h
Bit Attr
Reset
Value
Description