Datasheet

Processor Integrated I/O (IIO) Configuration Registers
240 Datasheet, Volume 2
3.3.8.3 VTD0_EXT_CAP—Extended Intel
®
VT-d Capability Register
7RO0b
CM
The processor does not cache invalid pages.
This bit should always be set to 0 on hardware. It can be set to 1 when doing
software virtualization of Intel VT-d.
6RO1b
PHMR Support
The processor supports protected high memory range.
5RO1b
PLMR Support
The processor supports protected low memory range.
4RO0b
RWBF
Not applicable for the processor.
3RO0b
Advanced Fault Logging
The processor does not support advanced fault logging.
2:0 RO 010b
Number of Domains Supported
The processor supports 256 domains with 8 bit domain ID.
VTD0_EXT_CAP
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 10h
Bit Attr
Reset
Value
Description
63:24 RV 0h Reserved
23:20 RO Fh
Maximum Handle Mask Value
IIO supports all 16 bits of handle being masked.
Note: IIO always performs global interrupt entry invalidation on any interrupt
cache invalidation command and hardware never really looks at the mask value.
19:18 RV 0h Reserved
17:8 RO 20h
Invalidation Unit Offset
IIO has the invalidation registers at offset 200h.
7RWO 1b
Snoop Control
0 = Hardware does not support 1-setting of the SNP field in the page-table
entries.
1 = Hardware supports the 1-setting of the SNP field in the page-table entries.
IIO supports snoop override only for the non-isoch Intel VT-d engine.
6RW-O 1b
Pass through
IIO supports pass through. This bit is RW-O for defeaturing in case of post-si
bugs.
5RO1b
Caching Hints
IIO supports caching hints
4RO1b
IA32 Extended Interrupt Mode
IIO supports the extended interrupt mode
3RWO 1b
Interrupt Remapping Support
IIO supports this
2RW-O 1b
Device TLB Support
IIO supports ATS for the non-isoch Intel VT-d engine. This bit is RW-O for non-
isoch engine in case we might have to defeature ATS post-si.
VTD0_CAP
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 8h
Bit Attr
Reset
Value
Description