Datasheet

Datasheet, Volume 2 239
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Processor Integrated I/O (IIO) Configuration Registers
3.3.8.1 VTD0_VERSION—Version Number Register
3.3.8.2 VTD0_CAP—Intel
®
VT-d Capabilities Register
VTD0_VERSION
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 0h
Bit Attr
Reset
Value
Description
31:8 RV 0h Reserved
7:4 RO 1h Major Revision
3:0 RO 0h Minor Revision
VTD0_CAP
Bus: 0 Device: 5 Function: 0 MMIO BAR: VTBAR
Offset: 8h
Bit Attr
Reset
Value
Description
63:56 RV 0h Reserved
55 RO 1b
DMA Read Draining
The processor supports hardware based draining
54 RO 1b
DMA Write Draining
The processor supports hardware based write draining
53:48 RO 12h
MAMV
The processor support MAMV value of 12h (up to 1G super pages).
47:40 RO 07h
Number of Fault Recording Registers
The processor supports 8 fault recording registers
39 RO 1b
Page Selective Invalidation
Supported in IIO
38 RV 0h Reserved
37:34 RWO 3h
Super Page Support
2 MB, 1G supported.
33:24 RO 10h
Fault Recording Register Offset
Fault registers are at offset 100h
23 RW-O 0b
ISOCH
Remapping Engine has ISOCH Support.
Note: This bit used to be for "Spatial Separation". This is no longer the case.
22 RWO 1b
ZLR
ZLR: Zero-length DMA requests to write-only pages supported.
21:16 RO 2Fh
MGAW
This register is set by the processor-based on the setting of the GPA_LIMIT
register. The value is the same for both the Intel High Definition Audio and non-
Intel High Definition Audio engines. This is because the translation for Intel High
Definition Audio has been extended to be 4-level (instead of 3).
15:13 RV 0h Reserved
12:8 RO 04h
SAGAW
Supports 4-level walk on both Intel High Definition Audio and non-Intel High
Definition Audio engines.