Datasheet

Datasheet, Volume 2 233
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Processor Integrated I/O (IIO) Configuration Registers
3.3.8 Intel
®
VT-d Memory Mapped Register
Intel VT-d registers are all addressed using aligned DWord or aligned QWord accesses.
Any combination of bits is allowed within a DWord or QWord access. The Intel VT-d
remap engine registers corresponding to the non-Isochronous port represented by
Device 0, occupy the first 4 K of offset starting from the base address defined by
VTBAR register. The Intel VT-d Isochronous remap engine registers occupies the second
4 K of offset starting from the base address.
Figure 3-3. Base Address of Intel VT-d Remap Engines
Non-Isoch Intel VT-d
Isoch Intel VT-d
VT_BAR
VT_ BAR + 8 KB Total
VT_ BAR + 4 KB