Datasheet

Processor Integrated I/O (IIO) Configuration Registers
232 Datasheet, Volume 2
3.3.7.10 RTH[0:23]—Redirection Table High DWord Register
12 RO 0b
Delivery Status
When trigger mode is set to level and the entry is unmasked, this bit indicates the
state of the level interrupt. That is, 1b if interrupt is asserted; else 0b. When the
trigger mode is set to level but the entry is masked, this bit is always 0b. This bit
is always 0b when trigger mode is set to edge.
11 RW 0b
Destination Mode
0 - Physical1 - Logical
10:8 RW 0b
Delivery Mode
This field specifies how the APICs listed in the destination field should act upon
reception of the interrupt. Certain Delivery modes will only operate as intended
when used in conjunction with a specific trigger mode. The encodings are:
000 = Fixed: Trigger mode can be edge or level. Examine TM bit to determine.
001 = Lowest Priority: Trigger mode can be edge or level. Examine TM bit to
determine.
010 = SMI/PMI: Trigger mode is always edge and TM bit is ignored.
011 = Reserved
100 = NMI. Trigger mode is always edge and TM bit is ignored.
101 = INIT. Trigger mode is always edge and TM bit is ignored.
110 = Reserved
111 = ExtINT. Trigger mode is always edge and TM bit is ignored.
7:0 RW 0h
Vector
This field contains the interrupt vector for this interrupt
7:18 RV 0h Reserved
RTH[0:23]
Bus: 0 Device: 5 Function: 4 MMIO BAR: WINDOW_0
Offset: 11
Bit Attr
Reset
Value
Description
31:24 RW 00h
Destination ID
They are bits [19:12] of the MSI address.
23:16 RW 00h
Extended Destination ID
These bits become bits [11:4] of the MSI address.
15:0 RV 0h Reserved
7:32 RV 0h Reserved
RTL[0:23]
Bus: 0 Device: 5 Function: 4 MMIO BAR: WINDOW_0
Offset: 10
Bit Attr
Reset
Value
Description