Datasheet
Datasheet, Volume 2 229
Processor Integrated I/O (IIO) Configuration Registers
3.3.7.4 EOI Register
3.3.7.5 APICID Register
This register uniquely identifies an APIC in the system. This register is not used by
operating systems anymore and is still implemented in hardware because of FUD.
3.3.7.6 VER—Version Register
This register uniquely identifies an APIC in the system. This register is not used by
operating systems anymore and is still implemented in hardware because of FUD.
EOI
Bus: 0 Device: 5 Function: 4 MMIO BAR: MBAR
Offset: 40
Bit Attr
Reset
Value
Description
7:0 RW-L 00h
EOI
The EOI register is present to provide a mechanism to efficiently convert level
interrupts to edge triggered MSI interrupts. When a write is issued to this register,
the I/O(x)APIC will check the lower 8 bits written to this register, and compare it
with the vector field for each entry in the I/O Redirection Table. When a match is
found, the Remote_IRR bit for that I/O Redirection Entry will be cleared. If
multiple I/O Redirection entries, for any reason, assign the same vector, each of
those entries will have the Remote_IRR bit reset to 0. This will cause the
corresponding I/OxAPIC entries to resample their level interrupt inputs and if they
are still asserted, cause more MSI interrupt(s) (if unmasked) which will again set
the Remote_IRR bit.
Note: Locked in D3hot state
APICID
Bus: 0 Device: 5 Function: 4 MMIO BAR: WINDOW_0
Offset: 0
Bit Attr
Reset
Value
Description
27:24 RW 0b
APICID
Allows for up to 16 unique APIC IDs in the system.
23:0 RV 0h Reserved
7:28 RV 0h Reserved
VER
Bus: 0 Device: 5 Function: 4 MMIO BAR: WINDOW_0
Offset: 1
Bit Attr
Reset
Value
Description
23:16 RO 17h
Maximum Redirection Entries
This is the entry number of the highest entry in the redirection table. It is equal to
the number of interrupt inputs minus one. This field is hardwired to 17h to
indicate 24 interrupts.
15 RO 0b
IRQ Assertion Register Supported
This bit is set to 0 to indicate that this version of the I/OxAPIC does not implement
the IRQ Assertion register and does not allow PCI devices to write to it to cause
interrupts.
14:8 RV 0h Reserved
7:0 RO 20h
Version
This identifies the implementation version. This field is hardwired to 20h indicate
this is an I/OxAPIC.
7:24 RV 0h Reserved