Datasheet

Processor Integrated I/O (IIO) Configuration Registers
228 Datasheet, Volume 2
3.3.7.1 INDX—Index Register
The Index Register will select which indirect register appears in the window register to
be manipulated by software. Software will program this register to select the desired
APIC internal register.
3.3.7.2 WNDW—Window Register
3.3.7.3 PAR—Pin Assertion Register
INDX
Bus: 0 Device: 5 Function: 4 MMIO BAR: MBAR
Offset: 0
Bit Attr
Reset
Value
Description
7:0 RW-L 00h
Index
Indirect register to access.
Note: Locked in D3hot state.
WNDW
Bus: 0 Device: 5 Function: 4 MMIO BAR: MBAR
Offset: 10
Bit Attr
Reset
Value
Description
31:0 RW-LV
000000
00h
Data
Data to be written to the indirect register on writes, and location of read data from
the indirect register on reads.
Note: Locked in D3hot state.
PAR
Bus: 0 Device: 5 Function: 4 MMIO BAR: MBAR
Offset: 20
Bit Attr
Reset
Value
Description
7:0 RO 0h
Pin Assertion
IIO does not allow writes to the PAR to cause MSI interrupts.