Datasheet

Processor Integrated I/O (IIO) Configuration Registers

226 Datasheet, Volume 2

3.3.7 I/OxAPIC Memory Mapped Registers

I/OxAPIC has a direct memory mapped space. An index/data register pair is located

within the directed memory mapped region and is used to access the redirection table

entries. provides the direct memory mapped registers of the I/OxAPIC. The offsets

shown in the table are from the base address in either ABAR or MBAR or both. Accesses

to addresses beyond 40h return all 0s.

Only addresses up to offset FFh can be accessed using the ABAR register; whereas

offsets up to FFFh can be accessed using MBAR. Only aligned DWord reads and write

are allowed towards the I/OxAPIC memory space. Any other accesses will result in an

error.

Table 3-19. I/OxAPIC Direct Memory Mapped Registers

INDX 0h

WNDW 10h

14h

18h

1Ch

PAR 20h

24h

28h

2Ch

30h

34h

38h

3Ch

EOI 40h

44h

48h

4Ch

50h

54h

58h

5Ch

60h

64h