Datasheet

Processor Integrated I/O (IIO) Configuration Registers
220 Datasheet, Volume 2
3.3.6.7 PMCAP—Power Management Capabilities Register
3.3.6.8 PMCSR—Power Management Control and Status Register
PMCAP
Bus: 0 Device: 5 Function: 4 Offset: 6C
Bit Attr
Reset
Value
Description
31:27 RO 0h
PME Support
Bits 31, 30, and 27 must be set to 1 for PCI-PCI bridge structures representing
ports on root complexes.
26 RO 0b
D2 Support
I/OxAPIC does not support power management state D2.
25 RO 0b
D1 Support
I/OxAPIC does not support power management state D1.
24:22 RO 0h AUX Current
21 RO 0b Device Specific Initialization
20 RV 0h Reserved
19 RO 0b
PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
18:16 RW-O 011b
Version
This field is set to 3h (PM 1.2 compliant) as version number. The bits are RW-O to
make the version 2h incase legacy operating systems have any issues.
15:8 RO 00h
Next Capability Pointer
This is the last capability in the chain and hence set to 0.
7:0 RO 01h
Capability ID
This field provides the PM capability ID assigned by PCI-SIG.
PMCSR
Bus: 0 Device: 5 Function: 4 Offset: 70
Bit Attr
Reset
Value
Description
31:24 RO 00h
Data
Not relevant for I/OxAPIC
23 RO 0h
Bus Power/Clock Control Enable
Not relevant for I/OxAPIC
22 RO 0h
B2/B3 Support
Not relevant for I/OxAPIC
21:16 RV 0h Reserved
15 RO 0h
PME Status
Not relevant for I/OxAPIC
14:13 RO 0h
Data Scale
Not relevant for I/OxAPIC
12:9 RO 0h
Data Select
Not relevant for I/OxAPIC
8RO0h
PME Enable
Not relevant for I/OxAPIC
7:4 RV 0h Reserved