Datasheet

22 Datasheet, Volume 2
Function 4, Offset 00h–FCh
Memory Controller Channel 1 Thermal Control Registers: Bus N, Device 16,
Function 5, Offset 00h–FCh...............................................................................293
4-12 Memory Controller Channel 2 Thermal Control Registers: Bus N, Device 16,
Function 0, Offset 100h–1FCh 
Memory Controller Channel 3 Thermal Control Registers: Bus N, Device 16,
Function 1, Offset 100h–1FCh
Memory Controller Channel 0 Thermal Control Registers: Bus N, Device 16,
Function 4, Offset 100h–1FCh
Memory Controller Channel 1 Thermal Control Registers: Bus N, Device 16,
Function 5, Offset 100h–1FCh ...........................................................................294
4-13 Memory Controller Channel 2 DIMM Timing Registers: Bus N, Device 16,
Function 0, Offset 200h–2FCh 
Memory Controller Channel 3 DIMM Timing Registers: Bus N, Device 16,
Function 1, Offset 200h–2FCh
Memory Controller Channel 0 DIMM Timing Registers: Bus N, Device 16,
Function 4, Offset 200h–2FCh
Memory Controller Channel 1 DIMM Timing Registers: Bus N, Device 16,
Function 5, Offset 200h–2FCh ...........................................................................295
4-14 Memory Controller Channel 2 DIMM Timing Registers: Bus N, Device 16,
Function 0, Offset 300h–3FCh 
Memory Controller Channel 3 DIMM Timing Registers: Bus N, Device 16,
Function 1, Offset 300h–3FCh
Memory Controller Channel 0 DIMM Timing Registers: Bus N, Device 16,
Function 4, Offset 300h–3FCh
Memory Controller Channel 1 DIMM Timing Registers: Bus N, Device 16,
Function 5, Offset 300h–3FCh ...........................................................................296
4-15 Memory Controller Channel 2 DIMM Training Registers: Bus N, Device 16,
Function 0, Offset 400h–4FCh 
Memory Controller Channel 3 DIMM Training Registers: Bus N, Device 16,
Function 1, Offset 400h–4FCh
Memory Controller Channel 0 DIMM Training Registers: Bus N, Device 16,
Function 4, Offset 400h–4FCh
Memory Controller Channel 1 DIMM Training Registers: Bus N, Device 16,
Function 5, Offset 400h–4FCh ...........................................................................297
4-16 Memory Controller Channel 2 Error Registers: Bus N, Device 16, Function 2,
Offset 00h–FCh 
Memory Controller Channel 3 Error Registers: Bus N, Device 16, Function 3,
Offset 00h–FCh
Memory Controller Channel 0 Error Registers: Bus N, Device 16, Function 6,
Offset 00h–FCh
Memory Controller Channel 1 Error Registers: Bus N, Device 16, Function 7,
Offset 00h–FC.................................................................................................298
4-17 Memory Controller Channel 2 Error Registers: Bus N, Device 16, Function 2,
Offset 100h–1FCh 
Memory Controller Channel 3 Error Registers: Bus N, Device 16, Function 3,
Offset 100h–1FCh
Memory Controller Channel 0 Error Registers: Bus N, Device 16, Function 6,
Offset 100h–1FCh
Memory Controller Channel 1 Error Registers: Bus N, Device 16, Function 7,

Offset 100h–1FCh............................................................................................299
4-18 Memory Controller Channel 2 Error Registers: Bus N, Device 16, Function 2,
Offset 200h–2FCh 
Memory Controller Channel 3 Error Registers: Bus N, Device 16, Function 3,
Offset 200h–2FCh
Memory Controller Channel 0 Error Registers: Bus N, Device 16, Function 6,