Datasheet

Datasheet, Volume 2 219
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Processor Integrated I/O (IIO) Configuration Registers
3.3.6.4 INTL—Interrupt Line Register
3.3.6.5 INTPIN—Interrupt Pin Register - Others
3.3.6.6 ABAR—I/OxAPIC Alternate BAR Register
INTL
Bus: 0 Device: 5 Function: 4 Offset: 3C
Bit Attr
Reset
Value
Description
7:0 RO 00h
Interrupt Line
Not applicable for these devices
INTPIN
Bus: 0 Device: 5 Function: 4 Offset: 3D
Bit Attr
Reset
Value
Description
7:0 RO 00h
Interrupt Pin
Not applicable since these devices do not generate any interrupt on their own
ABAR
Bus: 0 Device: 5 Function: 4 Offset: 40
Bit Attr
Reset
Value
Description
15 RW 0b
ABAR Enable
When set, the range FECX_YZ00 to FECX_YZFF is enabled as an alternate access
method to the IOxAPIC registers and these addresses are claimed by the IIO’s
internal I/OxAPIC, regardless of the setting the MSE bit in the I/OxAPIC
configuration space. Bits ’XYZ’ are defined below.
Note: Any accesses using message channel or JTAG mini port to registers pointed
to by the ABAR address, are not gated by this bit being set. That is, even if this bit
is a 0, message channel accesses to the registers pointed to by ABAR address are
allowed/completed normally.
14:12 RO 0h Reserved
11:8 RW 0h
Base Address [19:16] (XBAD)
These bits determine the high order bits of the I/O APIC address map. When a
memory address is recognized by the IIO which matches FECX_YZ00-to-
FECX_YZFF, the IIO will respond to the cycle and access the internal I/O APIC.
7:4 RW 0h
Base Address [15:12] (YBAD)
These bits determine the low order bits of the I/O APIC address map. When a
memory address is recognized by the IIO which matches FECX_YZ00-to-
FECX_YZFF, the IIO will respond to the cycle and access the internal I/O APIC.
3:0 RW 0h
Base Address [11:8] (ZBAD)
These bits determine the low order bits of the I/O APIC address map. When a
memory address is recognized by the IIO which matches FECX_YZ00-to-
FECX_YZFF, the IIO will respond to the cycle and access the internal I/O APIC.