Datasheet

Processor Integrated I/O (IIO) Configuration Registers
218 Datasheet, Volume 2
3.3.6 IOxAPIC PCI Configuration Space
This section covers the I/OxAPIC related registers
3.3.6.1 MBAR—IOxAPIC Base Address Register
3.3.6.2 SVID—Subsystem Vendor ID Register
3.3.6.3 SDID—Subsystem Device ID Register
MBAR
Bus: 0 Device: 5 Function: 4 Offset: 10
Bit Attr
Reset
Value
Description
31:12 RW 0h
BAR
This marks the 4 KB aligned 32-bit base address for memory-mapped registers of
I/OxAPIC
Note: Any accesses using message channel or JTAG mini port to registers pointed
to by the MBAR address, are not gated by MSE bit (in PCICMD register) being set;
that is, even if MSE bit is a 0, message channel accesses to the registers pointed
to by MBAR address are allowed/completed normally.
11:4 RO 0h Reserved
3RO0b
Prefetchable
The IOxAPIC registers are not prefetchable.
2:1 RO 00b
Type
The IOAPIC registers can only be placed below 4G system address space.
0RO0b
Memory Space
This Base Address Register indicates memory space.
SVID
Bus: 0 Device: 5 Function: 4 Offset: 2C
Bit Attr
Reset
Value
Description
15:0 RW-O 8086h
Subsystem Vendor Identification Number.
The default value specifies Intel but can be set to any value once after reset.
SDID
Bus: 0 Device: 5 Function: 4 Offset: 2E
Bit Attr
Reset
Value
Description
15:0 RW-O 0000h
Subsystem Device Identification Number
Assigned by the subsystem vendor to uniquely identify the subsystem