Datasheet

Datasheet, Volume 2 217
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Processor Integrated I/O (IIO) Configuration Registers
3.3.5.37 MINFERRHDR_[0:3]—Miscellaneous Non-Fatal First Error 
Header 0 Log Register
3.3.5.38 MINNERRST—Miscellaneous Non-Fatal Next Error Status Register
3.3.5.39 MIERRCNTSEL—Miscellaneous Error Count Select Register
3.3.5.40 MIERRCNT—Miscellaneous Error Counter Register
MINFERRHDR_[0:3]
Bus: 0 Device: 5 Function: 2 Offset: 3A4, 3A8, 3AC, 3B0
Bit Attr
Reset
Value
Description
31:0 ROS-V
000000
00h
Header
MINNERRST
Bus: 0 Device: 5 Function: 2 Offset: 3B4
Bit Attr
Reset
Value
Description
31:11 RV 0h Reserved
10:0 ROS-V 000h Miscellaneous Error Status Log
MIERRCNTSEL
Bus: 0 Device: 5 Function: 2 Offset: 3BC
Bit Attr
Reset
Value
Description
31:5 RV 0h Reserved
4RW0bDFx Injected Error Count Select
3RW0bVPP Error Status Count Select
2RW0bJTAG Tap Port Status Count Select
1RW0b
SMBus Port Status Count Select
This bit has no effect.
0RW0bConfig Register Parity Error Count Select
MIERRCNT
Bus: 0 Device: 5 Function: 2 Offset: 3C0
Bit Attr
Reset
Value
Description
31:8 RV 0h Reserved
7RW1CS 0b
Error Accumulator Overflow
0 = No overflow occurred
1 = Error overflow.
The error count may not be valid.
6:0 RW1CS 00h
Error Accumulator
This counter accumulates errors that occur when the associated error type is
selected in the ERRCNTSEL register.
Notes:
1. This register is cleared by writing 7Fh.
2. Maximum counter available is 127d (7Fh).