Datasheet

Datasheet, Volume 2 215
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Processor Integrated I/O (IIO) Configuration Registers
3.3.5.30 IIOERRCNT—IIO Core Error Counter Register
3.3.5.31 MIERRST—Miscellaneous Error Status Register
3.3.5.32 MIERRCTL—Miscellaneous Error Control Register
IIOERRCNT
Bus: 0 Device: 5 Function: 2 Offset: 340
Bit Attr
Reset
Value
Description
31:8 RV 0h Reserved
7RW1CS 0b
Error Accumulator Overflow
0 = No overflow occurred
1 = Error overflow. The error count may not be valid.
6:0 RW1CS 00h
Error Accumulator
This counter accumulates errors that occur when the associated error type is
selected in the ERRCNTSEL register.
Notes:
1. This register is cleared by writing 7Fh.
2. Maximum counter available is 127d (7Fh).
MIERRST
Bus: 0 Device: 5 Function: 2 Offset: 380
Bit Attr
Reset
Value
Description
31:5 RV 0h Reserved
4RW1CS 0bDFx Injected Error
3RW1CS 0bVPP Error Status
2RW1CS 0bJTAG Tap Port Status
1RW1CS 0b
SMBus Port Status (not used)
This bit will never be set since there is no longer an SMBus slave device.
0RW1CS 0bConfig Register Parity Error
MIERRCTL
Bus: 0 Device: 5 Function: 2 Offset: 384
Bit Attr
Reset
Value
Description
31:5 RV 0h Reserved
4RWS0bDFx Injected Error Enable
3RWS0bVPP Error Status Enable
2RWS0bJTAG Tap Port Status Enable
1RWS0b
SMBus Port Status Enable
This bit has no effect.
0RWS0bConfig Register Parity Error Enable