Datasheet

Processor Integrated I/O (IIO) Configuration Registers
212 Datasheet, Volume 2
3.3.5.20 IRPP1ERRCNT—IRP Protocol Error Counter Register
3.3.5.21 IIOERRST—IIO Core Error Status Register
This register indicates the IIO internal core errors detected by the IIO error logic. An
individual error status bit that is set indicates that a particular error occurred; software
may clear an error status by writing a 1 to the respective bit. This register is sticky and
can only be reset by PWRGOOD. Clearing of the IIO**ERRST is done by clearing the
corresponding IIOERRST bits.
3.3.5.22 IIOERRCTL—IIO Core Error Control Register
This register controls the reporting of IIO internal core errors detected by the IIO error
logic. An individual error control bit that is cleared masks reporting of that a particular
error; software may set or clear the respective bit. This register is sticky and can only
be reset by PWRGOOD.
IRPP1ERRCNT
Bus: 0 Device: 5 Function: 2 Offset: 2EC
Bit Attr
Reset
Value
Description
31:8 RV 0h Reserved
7RW1CS0b
Error Accumulator Overflow
0 = No overflow occurred
1 = Error overflow. The error count may not be valid.
6:0 RW1CS 00h
Error Accumulator (Counter)
This counter accumulates errors that occur when the associated error type is
selected in the ERRCNTSEL register.
Notes:
1. This register is cleared by writing 7Fh.
2. Maximum counter available is 127d (7Fh)
IIOERRST
Bus: 0 Device: 5 Function: 2 Offset: 300
Bit Attr
Reset
Value
Description
31:7 RV 0h Reserved
6RW1CS0bOverflow/Underflow Error Status (C6)
5RW1CS0bCompleter Abort Error Status (C5)
4RW1CS0bMaster Abort Error Status (C4)
3:0 RV 0h Reserved
IIOERRCTL
Bus: 0 Device: 5 Function: 2 Offset: 304
Bit Attr
Reset
Value
Description
31:7 RV 0h Reserved
6RWS0bOverflow/Underflow Error Enable (C6)
5RWS0bCompleter Abort Error Enable (C5)
4RWS0bMaster Abort Error Enable (C4)
3:0 RV 0h Reserved