Datasheet

Datasheet, Volume 2 211
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Processor Integrated I/O (IIO) Configuration Registers
3.3.5.17 IRPP1NNERRST—IRP Protocol Non-Fatal NERR Status Register
The error status log indicates which error is causing the report of the next non-fatal
error event (any event that is not the first).
3.3.5.18 IRPP1NFERRHD[0:3]—IRP Protocol Non-Fatal FERR Header 
Log 0 Register
3.3.5.19 IRPP1ERRCNTSEL—IRP Protocol Error Counter Select Register
IRPP1NNERRST
Bus: 0 Device: 5 Function: 2 Offset: 2D4
Bit Attr
Reset
Value
Description
31:15 RV 0h Reserved
14 ROS-V 0b
Protocol Parity Error (DB)
This bit was originally used for detecting parity error on coherent interface:
however, no parity checks exist. Thus, this bit logs parity errors on data from the
IIO switch on the inbound path.
13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA)
12:11 RV 0h Reserved
10 ROS-V 0b
Protocol Layer Received Unexpected Response/Completion (D7)
A completion has been received from the Coherent Interface that was unexpected.
9:5 RV 0h Reserved
4ROS-V 0bCSR Access Crossing 32-bit Boundary (C3)
3ROS-V 0b
Write Cache Un-correctable ECC (C2)
A double bit ECC error was detected within the Write Cache.
2ROS-V 0b
Protocol Layer Received Poisoned Packet (C1)
A poisoned packet has been received from the Coherent Interface.
1ROS-V 0b
Write Cache Correctable ECC (B4)
A single bit ECC error was detected and corrected within the Write Cache.
0RV0hReserved
IRPP1NFERRHD[0:3]
Bus: 0 Device: 5 Function: 2 Offset: 2D8, 2DC, 2E0, 2E4
Bit Attr
Reset
Value
Description
31:0 ROS-V
000000
00h
Log of Header DWord 0
Logs the first DWord of the header on an error condition
IRPP1ERRCNTSEL
Bus: 0 Device: 5 Function: 2 Offset: 2E8
Bit Attr
Reset
Value
Description
31:19 RV 0h Reserved
18:0 RW 00000h
Select Error Events for Counting
See IRPP0ERRST for per bit description of each error. Each bit in this field has the
following behavior:
0 = Do not select this error type for error counting
1 = Select this error type for error counting