Datasheet

Datasheet, Volume 2 21
3-7 Device 0/Function 0 DMI2 mode), Devices 2/Functions 0 (PCIe* Root Port),
and Device 3/Function 0 (PCIe* Root Port) Extended Configuration Map –
Offset 400h–4FCh .............................................................................................46
3-8 DMI2 RCRB Registers....................................................................................... 134
3-9 Intel
®
VT, Address Map, System Management, Miscellaneous Registers 
(Device 5, Function 0) – Offset 000h–0FFh ......................................................... 145
3-10 Intel
®
VT-d, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) – Offset 100h–1FFh ......................................................... 146
3-11 Intel
®
VT-d, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) - Offset 200h-2FFh .......................................................... 147
3-12 Intel
®
VT-d, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) – Offset 800h–8FFh ......................................................... 148
3-13 IIO Control/Status and Global Error Register Map – Device 5, Function 2 –
Offset 0h–FFh................................................................................................. 149
3-14 IIO Control/Status and Global Error Register Map – Device 5, Function 2 –
Offset 100h–1FFh............................................................................................ 150
3-15 IIO Local Error Map – Device 5, Function 2 – Offset 200h–2FFh............................. 151
3-16 IIO Local Error Map – Device 5, Function 2 – Offset 300h–3FFh............................. 152
3-17 I/OxAPIC PCI Configuration Space Map – Device 5/Function 4 – 
Offset 00h–FFh ............................................................................................... 153
3-18 I/OxAPIC PCI Configuration Space Map – Device 5/Function 4 – 
Offset 200h–2FFh............................................................................................ 154
3-19 I/OxAPIC Direct Memory Mapped Registers......................................................... 226
3-20 I/OxAPIC Indexed Registers (Redirection Table Entries) – WINDOW 0 –
Register Map Table.......................................................................................... 227
3-21 Intel
®
VT-d Memory Mapped Registers – 00h–FFh (VTD0) .................................... 234
3-22 Intel
®
VT-d Memory Mapped Registers – 100h–1FCh (VTD0) ................................ 235
3-23 Intel
®
VT-d Memory Mapped Registers – 200h–2FCh (VTD0), 1200h–12FCh (VTD1) 236
3-24 Intel
®
VT-d Memory Mapped Registers – 1000h–11FCh (VTD1)............................. 237
3-25 Intel
®
VT-d Memory Mapped Registers – 1100h–11FCh (VTD1)............................. 238
4-1 Unicast CSR’s(CBo) : Device 12–13, Function 0–3, Offset 00h–FCh........................ 283
4-2 System Address Decoder (CBo) : Device 12, Function 6, Offset 00h–FCh ................ 284
4-3 Caching agent broadcast registers(CBo) : Device 12, Function 7, 
Offset 00h–FCh............................................................................................... 285
4-4 Caching agent broadcast registers(CBo): Device 13, Function 6, 
Offset 00h–FCh............................................................................................... 286
4-5 Memory Controller Target Address Decoder Registers: Device 15, 
Function 0, Offset 00h–FCh .............................................................................. 287
4-6 Memory Controller MemHot and SMBus Registers: Bus N, Device 15, 
Function 0, Offset 100h–1FCh........................................................................... 288
4-7 Memory Controller RAS Registers: Bus N, Device 15, Function 1, 
Offset 00h–FCh............................................................................................... 289
4-8 Memory Controller RAS Registers: Bus N, Device 15, Function 1, 
Offset 100h–1FCh ........................................................................................... 290
4-9 Memory Controller DIMM Timing and Interleave Registers: Bus N, 
Device 15, Function 2–5 Offset 00h–FCh ............................................................ 291
4-10 Memory Controller Channel Rank Registers: Bus N, Device 15, 
Function 2–5 Offset 100h–1FCh ........................................................................ 292
4-11 Memory Controller Channel 2 Thermal Control Registers: Bus N, Device 16,
Function 0, Offset 00h–FCh 
Memory Controller Channel 3 Thermal Control Registers: Bus N, Device 16,
Function 1, Offset 00h–FCh
Memory Controller Channel 0 Thermal Control Registers: Bus N, Device 16,