Datasheet

Processor Integrated I/O (IIO) Configuration Registers
208 Datasheet, Volume 2
3.3.5.12 IRPP1ERRCTL—IRP Protocol Error Control Register
This register enables the error status bit setting for a Coherent Interface detected error.
Setting of the bit enables the setting of the corresponding error status bit in IRPPERRST
register. If the bit is cleared, the corresponding error status will not be set.
IRPP1ERRCTL
Bus: 0 Device: 5 Function: 2 Offset: 2B4
Bit Attr
Reset
Value
Description
31:15 RV 0h Reserved
14 RWS 0b
Protocol Parity Error (DB)
0 = Disable error status logging for this error
1 = Enable Error status logging for this error
13 RWS 0b
Protocol Queue/Table Overflow or Underflow (DA)
0 = Disable error status logging for this error
1 = Enable Error status logging for this error
12:11 RV 0h Reserved
10 RWS 0b
Protocol Layer Received Unexpected Response/Completion (D7)
0 = Disable error status logging for this error
1 = Enable Error status logging for this error
9:5 RV 0h Reserved
4RWS0b
CSR Access Crossing 32-bit Boundary (C3)
0 = Disable error status logging for this error
1 = Enable Error status logging for this error
3RWS0b
Write Cache Un-correctable ECC (C2)
0 = Disable error status logging for this error
1 = Enable Error status logging for this error
2RWS0b
Protocol Layer Received Poisoned Packet (C1)
0 = Disable error status logging for this error
1 = Enable Error status logging for this error
1RWS0b
Write Cache Correctable ECC (B4)
0 = Disable error status logging for this error
1 = Enable Error status logging for this error
0RV0hReserved