Datasheet

Datasheet, Volume 2 207
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Processor Integrated I/O (IIO) Configuration Registers
3.3.5.11 IRPP1ERRST—IRP Protocol Error Status Register
This register indicates the error detected by the Coherent Interface.
IRPP1ERRST
Bus: 0 Device: 5 Function: 2 Offset: 2B0
Bit Attr
Reset
Value
Description
31:15 RV 0h Reserved
14 RW1CS 0b
Protocol Parity Error (DB)
This bit was originally used for detecting parity error on coherent interface;
however, no parity checks exist. Thus, this bit logs parity errors on data from the
IIO switch on the inbound path.
13 RW1CS 0b Protocol Queue/Table Overflow or Underflow (DA)
12:11 RV 0h Reserved
10 RW1CS 0b
Protocol Layer Received Unexpected Response/Completion (D7)
A completion has been received from the Coherent Interface that was unexpected.
9:5 RV 0h Reserved
4RW1CS 0bCSR Access Crossing 32-bit Boundary (C3)
3RW1CS 0b
Write Cache Un-correctable ECC (C2)
A double bit ECC error was detected within the Write Cache.
2RW1CS 0b
Protocol Layer Received Poisoned Packet (C1)
A poisoned packet has been received from the Coherent Interface.
1RW1CS 0b
Write Cache Correctable ECC (B4)
A single bit ECC error was detected and corrected within the Write Cache.
0RV0hReserved