Datasheet

Processor Integrated I/O (IIO) Configuration Registers
206 Datasheet, Volume 2
3.3.5.8 IRPP0NFERRHD[0:3]—IRP Protocol Non-Fatal FERR Header 
Log 0 Register
3.3.5.9 IRPP0ERRCNTSEL—IRP Protocol Error Counter Select Register
3.3.5.10 IRPP0ERRCNT—IRP Protocol Error Counter Register
1ROS-V0b
Write Cache Correctable ECC (B4)
A single bit ECC error was detected and corrected within the Write Cache.
0RV0hReserved
IRPP0NFERRHD[0:3]
Bus: 0 Device: 5 Function: 2 Offset: 258, 25C, 260, 264
Bit Attr
Reset
Value
Description
31:0 ROS-V
000000
00h
Log of Header DWord 0
Logs the first DWord of the header on an error condition
IRPP0ERRCNTSEL
Bus: 0 Device: 5 Function: 2 Offset: 268
Bit Attr
Reset
Value
Description
31:19 RV 0h Reserved
18:0 RW 00000h
Select Error Events for Counting
See IRPP0ERRST for per bit description of each error. Each bit in this field has the
following behavior:
0 = Do not select this error type for error counting
1 = Select this error type for error counting
IRPP0ERRCNT
Bus: 0 Device: 5 Function: 2 Offset: 26C
Bit Attr
Reset
Value
Description
31:8 RV 0h Reserved
7RW1CS0b
ERROVF: Error Accumulator Overflow
0 = No overflow occurred
1 = Error overflow. The error count may not be valid.
6:0 RW1CS 00h
Error Accumulator (Counter)
This counter accumulates errors that occur when the associated error type is
selected in the ERRCNTSEL register.
Notes:
1. This register is cleared by writing 7Fh.
2. Maximum counter available is 127d (7Fh)
IRPP0NNERRST
Bus: 0 Device: 5 Function: 2 Offset: 254
Bit Attr
Reset
Value
Description