Datasheet

Processor Integrated I/O (IIO) Configuration Registers
204 Datasheet, Volume 2
3.3.5.4 IRPP0FNERRST—IRP Protocol Fatal NERR Status Register
The error status log indicates which error is causing the report of the next fatal error
event (any event that is not the first).
3.3.5.5 IRPP0FFERRHD[0:3]—IRP Protocol Fatal FERR Header 
Log 0 Register
IRPP0FNERRST
Bus: 0 Device: 5 Function: 2 Offset: 23C
Bit Attr
Reset
Value
Description
31:15 RV 0h Reserved
14 ROS-V 0b
Protocol Parity Error (DB)
This bit was originally used for detecting parity error on coherent interface;
however, no parity checks exist. Thus, this logs parity errors on data from the IIO
switch on the inbound path.
13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA)
12:11 RV 0h Reserved
10 ROS-V 0b
Protocol Layer Received Unexpected Response/Completion (D7)
A completion has been received from the Coherent Interface that was unexpected.
9:5 RV 0h Reserved
4ROS-V0bCSR Access Crossing 32-bit Boundary (C3)
3ROS-V0b
Write Cache Un-correctable ECC (C2)
A double bit ECC error was detected within the Write Cache.
2ROS-V0b
Protocol Layer Received Poisoned Packet (C1)
A poisoned packet has been received from the Coherent Interface.
1ROS-V0b
Write Cache Correctable ECC (B4)
A single bit ECC error was detected and corrected within the Write Cache.
0RV0hReserved
IRPP0FFERRHD[0:3]
Bus: 0 Device: 5 Function: 2 Offset: 240, 244, 248, 24C
Bit Attr
Reset
Value
Description
31:0 ROS-V
000000
00h
Log of Header DWord 0
Logs the first DWord of the header on an error condition