Datasheet

Datasheet, Volume 2 201
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Processor Integrated I/O (IIO) Configuration Registers
3.3.4.18 GFNERRST—Global Fatal NERR Status Register
3.3.4.19 GNFERRST—Global Non-Fatal FERR Status Register
3.3.4.20 GNNERRST—Global Non-Fatal NERR Status Register
GFNERRST
Bus: 0 Device: 5 Function: 2 Offset: 1E8
Bit Attr
Reset
Value
Description
31:27 RV 0h Reserved
26:0 ROS-V
000000
0h
Global Error Status Log
This filed logs the global error status register content when the next fatal error is
reported. This has the same format as the global error status register (GFERRST).
GNFERRST
Bus: 0 Device: 5 Function: 2 Offset: 1EC
Bit Attr
Reset
Value
Description
31:27 RV 0h Reserved
26:0 ROS-V
000000
0h
Global Error Status Log
This filed logs the global error status register content when the first non-fatal
error is reported. This has the same format as the global error status register
(GNERRST).
GNNERRST
Bus: 0 Device: 5 Function: 2 Offset: 1F8
Bit Attr
Reset
Value
Description
31:27 RV 0h Reserved
26:0 ROS-V
000000
0h
Global Error Status Log
This filed logs the global error status register content when the subsequent non-
fatal error is reported. This has the same format as the global error status register
(GNERRST).