Datasheet

Processor Integrated I/O (IIO) Configuration Registers
200 Datasheet, Volume 2
3.3.4.15 GSYSST—Global System Event Status Register
This register indicates the error severity signaled by the IIO global error logic. Setting
of an individual error status bit indicates that the corresponding error severity has been
detected by the IIO.
3.3.4.16 GSYSCTL—Global System Event Control Register
The system event control register controls/masks the reporting the errors indicated by
the system event status register. When cleared, the error severity does not cause the
generation of the system event. When set, detection of the error severity generates
system event(s) according to system event map register (SYSMAP).
3.3.4.17 GFFERRST—Global Fatal FERR Status Register
GSYSST
Bus: 0 Device: 5 Function: 2 Offset: 1CC
Bit Attr
Reset
Value
Description
31:5 RV 0h Reserved
4ROS-V0b
Severity Error 4 Thermal Trip
Thermal Trip Error (not used in the processor)
3ROS-V0b
Severity 3 Thermal Alert
Thermal Alert Error (not used in the processor)
2ROS-V0b
Severity 2 Error Status
When set, IIO has detected an error of error severity 2
1ROS-V0b
Severity 1 Error Status
When set, IIO has detected an error of error severity 1
0ROS-V0b
Severity 0 Error Status
When set, IIO has detected an error of error severity 0
GSYSCTL
Bus: 0 Device: 5 Function: 2 Offset: 1D0
Bit Attr
Reset
Value
Description
31:5 RV 0h Reserved
4RW0b
Severity 4 Enable Thermal Trip
Thermal Trip Enable (not used in the processor)
3RW0b
Severity 3 Enable Thermal Alert
Thermal Alert Enable (not used in the processor)
2RW0bSeverity 2 Error Enable
1RW0bSeverity 1 Error Enable
0RW0bSeverity 0 Error Enable
GFFERRST
Bus: 0 Device: 5 Function: 2 Offset: 1DC
Bit Attr
Reset
Value
Description
31:27 RV 0h Reserved
26:0 ROS-V
000000
0h
Global Error Status Log
This field logs the global error status register content when the first fatal error is
reported. This has the same format as the global error status register (GFERRST).