Datasheet

20 Datasheet, Volume 2
4.8.7 DDRIOTXTopRank0A[0:1]—DDRIOTXTopRank0 Register............................547
4.8.8 DDRIOCtlPICode0A[0:1]—DDRIOCtlPICode0 Register ................................548
4.8.9 DDRIOCtlPICode1A[0:1]—DDRIOCtlPICode1 Register ................................549
4.8.10 DDRIOLogicDelayA[0:1]—DDRIOLogicDelay Register.................................550
4.8.11 DDRIOCtlRankCnfgA[0:1]—DDRIOCtlRankCnfg Register.............................550
4.8.12 DDRIOCmdPICodeA[0:1]—DDRIOCmdPICode Register...............................551
4.8.13 DDRIOCkRankUsedA[0:1]—DDRIOCkRankUsed Register ............................552
4.8.14 DDRIOCkPiCode0A[0:1]—DDRIOCkPiCode0 Register .................................553
4.8.15 DDRIOCkPiCode1A[0:1]—DDRIOCkPiCode1 Register .................................554
4.8.16 DDRIOCkLogicDelayA[0:1]—DDRIOCkLogicDelay Register..........................555
4.8.17 DDRIOCompOvrOfst2A[0:1]—
DDRIOCompOvrOfst2 Register................................................................555
4.8.18 DDRIOCompOVR5A[0:1] Register ...........................................................556
4.8.19 DDRIOCompCfgSPDA[0:1] Register.........................................................557
4.8.20 QPIREUT_PM_R0—REUT Power Management Register 0.............................558
4.8.21 TXALIGN_EN Register............................................................................560
4.8.22 TXEQ_LVL0_0 Register ..........................................................................561
4.8.23 TXEQ_LVL0_1 Register ..........................................................................561
4.8.24 TXEQ_LVL1_0 Register ..........................................................................561
4.8.25 TXEQ_LVL1_1 Register ..........................................................................562
4.8.26 TXEQ_LVL2_0 Register ..........................................................................562
4.8.27 TXEQ_LVL2_1 Register ..........................................................................562
4.8.28 TXEQ_LVL3_0 Register ..........................................................................563
4.8.29 FWDC_LCPKAMP_CFG Register...............................................................563
Figures
2-1 Processor Integrated I/O Device Map....................................................................31
2-2 Processor Uncore Devices Map.............................................................................33
3-1 DMI2 Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space..........38
3-2 Device 1/Functions 0–1 (Root Ports) – Device 2/Function 0–3 (Root Port
Mode) and Devices 3/Functions 0–3 (Root Ports) Type 1 Configuration Space ............39
3-3 Base Address of Intel VT-d Remap Engines233
Tables
1-1 Processor Terminology .......................................................................................25
1-2 Processor Documents.........................................................................................27
1-3 Register Attributes Definitions .............................................................................28
2-1 Functions Specifically Handled by the Processor.....................................................35
3-1 (DMI2 Mode) Legacy Configuration Map – Device 0 Function 0 – 
Offset 00h–0FCh................................................................................................40
3-2 (DMI2) Extended Configuration Map – Device 0/Function 0 – 
Offset 100h–1FCh..............................................................................................41
3-3 (DMI2) Mode Extended Configuration Map – Device 0/Function 0 – 
Offset 200h–2FCh..............................................................................................42
3-4 Device 1/Functions 0-1 (PCIe* Root Ports), Devices 2/Functions 0–3 
(PCIe* Root Ports), and Device 3/Function 0–3 (PCIe* Root Ports) 
Legacy Configuration Map...................................................................................43
3-5 Device 1/Functions 0–1 (PCIe* Root Ports), Devices 2/Functions 0–3 
(PCIe* Root Ports), Device 3/Function 0-3 (PCIe* Root Ports) Extended
Configuration Map – Offset 100h–1FFh .................................................................44
3-6 Device 1/Functions 0-1 (PCIe* Root Ports), Devices 2/Functions 0–3 
(PCIe* Root Ports), and Device 3/Function 0–3 (PCIe* Root Ports)
Extended Configuration Map – Offset 200h–2FCh...................................................45