Datasheet

Datasheet, Volume 2 199
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Processor Integrated I/O (IIO) Configuration Registers
3.3.4.14 GERRCTL—Global Error Control Register
This register controls/masks the reporting of errors detected by the IIO local interfaces.
An individual error control bit that is set masks error reporting of the particular local
interface; software may set or clear the control bit. This register is sticky and can only
be reset by PWRGOOD. Note that bit fields in this register can become reserved
depending on the port configuration. For example, if the PCIe port is configured as 2X8
ports, then only the corresponding PCIe X8 bit fields are valid; other bits are unused
and reserved. Global error control register masks errors reported from the local
interface to the global register. If the an error reporting is disabled in this register, all
errors from the corresponding local interface will not set any of the global error status
bits.
GERRCTL
Bus: 0 Device: 5 Function: 2 Offset: 1C8
Bit Attr
Reset
Value
Description
31:26 RV 0h Reserved
25 RW 0b VTd Error Mask
24 RW 0b Miscellaneous Error Mask
23 RW 0b
IIO Core Error Enable
This bit enables/masks the error detected in the IIO Core.
22 RW 0b
DMA Error Enable
This bit enables/masks the error detected in the DMA .
21 RV 0h Reserved
20 RW 0b
DMI Error Enable
This bit enables/masks the error detected in the DMI[0] Port.
19:16 RV 0h Reserved
15:5 RW 000h
PCIe Error Mask
Masks the error detected with the associated PCIe port.
Bit 5 = Port 0
Bit 6 = Port 1a
Bit 7 = Port 1b
Bit 8 = Port 2a
Bit 9 = Port 2b
Bit 10 = Port 2c
Bit 11 = Port 2d
Bit 12 = Port 3a
Bit 13 = Port 3b
Bit 14 = Port 3c
Bit 15 = Port 3d
4:2 RV 0h Reserved
1RW0bIRP1 Error Mask
0RW0b
IRP0 Error Mask
When set, disables logging of this error