Datasheet

Processor Integrated I/O (IIO) Configuration Registers
198 Datasheet, Volume 2
3.3.4.13 GFERRST—Global Fatal Error Status Register
This register indicates the fatal error reported to the IIO global error logic. An individual
error status bit that is set indicates that a particular local interface has detected an
error.
GFERRST
Bus: 0 Device: 5 Function: 2 Offset: 1C4
Bit Attr
Reset
Value
Description
31:26 RV 0h Reserved
25 RW1CS 0b
Intel VT-d Error Status
This register indicates the fatal error reported to the Intel VT-d error logic. An
individual error status bit that is set indicates that a particular local interface has
detected an error.
24 RV 0h Reserved
23 RW1CS 0b
IIO Core Error Status
This bit indicates that IIO core has detected an error.
22 RW1CS 0b
DMA Error Status
This bit indicates that IIO has detected an error in its DMA engine.
21 RV 0h Reserved
20 RW1CS 0b
DMI Error Status
This bit indicates that IIO DMI port 0 has detected an error.
19:16 RV 0h Reserved
15:5 RW1CS 000h
PCIe Error Status
Associated PCIe logical port has detected an error.
Bit 5 = Port 0
Bit 6 = Port 1a
Bit 7 = Port 1b
Bit 8 = Port 2a
Bit 9 = Port 2b
Bit 10 = Port 2c
Bit 11 = Port 2d
Bit 12 = Port 3a
Bit 13 = Port 3b
Bit 14 = Port 3c
Bit 15 = Port 3d
4:2 RV 0h Reserved
1RW1CS0bIRP1 Coherent Interface Error
0RW1CS0bIRP0 Coherent Interface Error