Datasheet

Processor Integrated I/O (IIO) Configuration Registers
196 Datasheet, Volume 2
3.3.4.10 VPPCTL—VPP Control Register
This register defines the control/command for PCA9555.
3.3.4.11 VPPSTS—VPP Status Register
This register defines the status from PCA9555.
VPPCTL
Bus: 0 Device: 5 Function: 2 Offset: B0
Bit Attr
Reset
Value
Description
63:56 RV 0h Reserved
55 RWS 0b
VPP Reset Mode
0 = Power good reset will reset the VPP state machines and hard reset will cause
the VPP state machine to terminate at the next ’logical’ VPP stream boundary
and then reset the VPP state machines
1 = Both power good and hard reset will reset the VPP state machines
54:44 RWS 000h
VPP Enable
When set, the VPP function for the corresponding root port is enabled.
Enable Root Port
[54] Port 3d
[53] Port 3c
[52] Port 3b
[51] Port 3a
[50] Port 2d
[49] Port 2c
[48] Port 2b
[47] Port 2a
[46] Port 1b
[45] Port 1a
[44] Port 0 (PCIe mode only)
43:0 RWS
000000
00000h
VPP Address
This field assigns the VPP address of the device on the VPP interface and assigns
the port address for the ports within the VPP device. There are more address bits
than root ports so assignment must be spread across VPP ports.
Port Addr Root Port
[43] [42:40] Port 3d
[39] [38:36] Port 3c
[35] [34:32] Port 3b
[31] [30:28] Port 3a
[27] [27:24] Port 2d
[23] [22:20] Port 2c
[19] [18:16] Port 2b
[15] [14:12] Port 2a
[11] [10:8] Port 1b
[7] [6:4] Port 1a
[3] [2:0] Port 0 (PCIe mode only)
VPPSTS
Bus: 0 Device: 5 Function: 2 Offset: B8
Bit Attr
Reset
Value
Description
31:1 RV 0h Reserved
0 RW1CS 00b
VPP Error
VPP Port error happened; that is, an unexpected STOP of NACK was seen on the
VPP port.