Datasheet
Processor Integrated I/O (IIO) Configuration Registers
194 Datasheet, Volume 2
3.3.4.6 VIRAL—Viral Alert Register
This register provides the option to generate viral alert upon the detection of fatal error.
Viral is not officially supported in the processor but am still leaving it in here because
IVB might need it.
3.3.4.7 ERRPINCTL—Error Pin Control Register
This register provides the option to configure an error pin to either as a special purpose
error pin that is asserted based on the detected error severity, or as a general purpose
output that is asserted based on the value in the ERRPINDAT. The assertion of the error
pins can also be completely disabled by this register.
VIRAL
Bus: 0 Device: 5 Function: 2 Offset: A0
Bit Attr
Reset
Value
Description
31:3 RV 0h Reserved
2RWS0b
Fatal Viral Alert Enable
This bit enables viral alert for Fatal Error.
0 = Disable Viral Alert for error severity 2.
1 = IIO goes viral when error severity 2 is set in the system event status register.
Notes:
1. Recommendation is for BIOS to leave this bit at 0 always.
2. This is unsupported in the processor
1:0 RV 0h Reserved
ERRPINCTL
Bus: 0 Device: 5 Function: 2 Offset: A4
Bit Attr
Reset
Value
Description
31:6 RV 0h Reserved
5:4 RW 00b
Error[2] Pin Assertion Control
11 = Reserved
10 = Assert Error Pin when error severity 2 is set in the system event status reg.
01 = Assert and Deassert Error pin according to error pin data register.
00 = Disable Error pin assertion
3:2 RW 00b
Error[1] Pin Assertion Control
11 = Reserved
10 = Assert Error Pin when error severity 1 is set in the system event status reg.
01 = Assert and Deassert Error pin according to error pin data register.
00 = Disable Error pin assertion
1:0 RW 00b
Error[0] Pin Assertion Control
11 = Reserved
10 = Assert Error Pin when error severity 0 is set in the system event status reg.
01 = Assert and Deassert Error pin according to error pin data register.
00 = Disable Error pin assertion