Datasheet
Datasheet, Volume 2 19
4.5.2.7 UBOXErrSts—Error Status Register............................................ 522
4.5.2.8 EVENTS_DEBUG Register......................................................... 523
4.5.3 ScratchPad and Semaphore Registers ..................................................... 523
4.5.3.1 BIOSScratchpad[0:7]—BIOS Scratchpad 0 Register..................... 523
4.5.3.2 BIOSNonStickyScratchpad[0:15]—BIOS NonSticky
Scratchpad 0 Register ............................................................. 523
4.5.3.3 LocalSemaphore[0:1]—Local Semaphore 0 Register .................... 524
4.5.3.4 SystemSemaphore[0:1]—System Semaphore 0 Register.............. 525
4.5.3.5 DEVHIDE[0:7]—Device Hide 0 Register...................................... 526
4.5.3.6 CPUBUSNO—CPU Bus Number Register...................................... 526
4.5.3.7 SMICtrl—SMI Control Register .................................................. 526
4.5.3.8 ABORTDEBUG1—Abort Debug Register ...................................... 527
4.5.3.9 ABORTDEBUG2—Abort Debug Register ...................................... 527
4.6 Performance Monitoring (PMON) Registers.......................................................... 528
4.6.1 CSR Register Maps ............................................................................... 528
4.6.2 Processor Performance Monitor Registers................................................. 529
4.6.2.1 PmonCtr[0:4]—PMON Counter.................................................. 529
4.6.2.2 PmonDbgCntResetVal—Perfmon Counter 4 Reset Value
Register................................................................................. 529
4.6.2.3 PmonCntr_Fixed—Fixed Counter Register................................... 529
4.6.2.4 PmonCntrCfg_[0:4]—Performance Counter Control Register ......... 530
4.6.2.5 PmonUnitCtrl—Performance Unit Control Register........................ 531
4.6.2.6 PmonUnitStatus—Performance Unit Status Register..................... 532
4.6.2.7 HaPerfmonAddrMatch0—
Home Agent Perfmon Address Match Register 0 .......................... 533
4.6.2.8 HaPerfmonAddrMatch1—
Home Agent Perfmon Address Match Register 1 .......................... 533
4.6.2.9 HaPerfmonOpcodeMatch—HA Performance Opcode Match Register 533
4.6.2.10 HAPmonDbgCtrl—HA Perfmon Debug Control Register ................. 534
4.6.2.11 HAPmonDbgCntResetVal—Perfmon Counter 4 Reset
Value Register........................................................................ 534
4.7 R2PCIe Routing Table and Ring Credits .............................................................. 535
4.7.1 R2PCIe Routing Register Map................................................................. 535
4.7.1.1 IIO_BW_COUNTER—IIO Bandwidth Counter Register................... 536
4.7.1.2 R2PGNCTRL—R2PCIe General Control Register............................ 536
4.7.1.3 R2PINGERRLOG0 Register........................................................ 536
4.7.1.4 R2PINGERRMSK0 Register........................................................ 537
4.7.1.5 R2PINGDBG Register............................................................... 537
4.7.1.6 R2PEGRDBG Register .............................................................. 538
4.7.1.7 R2PDEBUG—R2PCIe Debug Register.......................................... 538
4.7.1.8 R2EGRERRLOG Register........................................................... 539
4.7.1.9 R2EGRERRMSK Register .......................................................... 540
4.7.1.10 R2PCIE_DBG_BUS_CONTROL Register....................................... 541
4.7.1.11 R2PCIE_DBG_BUS_MATCH Register .......................................... 541
4.7.1.12 R2PCIE_DBG_BUS_MASK Register ............................................ 541
4.7.1.13 R2PCIE_ASC_CNTR Register..................................................... 541
4.7.1.14 R2PCIE_ASC_LDVAL Register ................................................... 542
4.7.1.15 R2PCIE_ASC_CONTROL Register............................................... 542
4.7.1.16 R2PCIE_GLB_RSP_CNTRL Register............................................ 542
4.7.1.17 R2PCIE_LCL_RESP_CNTRL Register........................................... 542
4.8 MISC Registers ............................................................................................... 543
4.8.1 DDRIOTrainingModeA[0:1]—DDRIOTrainingMode Register ......................... 543
4.8.2 DDRIOTrainingResult1A[0:1]—
DDRIOTrainingResult1 Register.............................................................. 544
4.8.3 DDRIOTrainingResult2A[0:1]—
DDRIOTrainingResult2 Register.............................................................. 544
4.8.4 DDRIOBuffCfgA[0:1]—DDRIOBuffCfg Register.......................................... 545
4.8.5 DDRIOTXRXBotRank0A[0:1]—
DDRIOTXRXBotRank0 Register............................................................... 546
4.8.6 DDRIORXTopRank0A[0:1]—DDRIORXTopRank0 Register ........................... 547