Datasheet

Processor Integrated I/O (IIO) Configuration Registers
184 Datasheet, Volume 2
3.3.3.37 IRP0DELS—Coherent Interface 0 Debug Event Lane 
Select Register
3.3.3.38 IRP1DELS—Coherent Interface 1 Debug Event Lane 
Select Register
IRP0DELS
Bus: 0 Device: 5 Function: 0 Offset: 808
Bit Attr
Reset
Value
Description
63:36 RV 0h Reserved
35:32 RW-L 0h
Debug Event Set Lane Select 8
Note: Locked by DBGBUSLCK
31:28 RW-L 0h
Debug Event Set Lane Select 7
Note: Locked by DBGBUSLCK
27:24 RW-L 0h
Debug Event Set Lane Select 6
Note: Locked by DBGBUSLCK
23:20 RW-L 0h
Debug Event Set Lane Select 5
Note: Locked by DBGBUSLCK
19:16 RW-L 0h
Debug Event Set Lane Select 4
Note: Locked by DBGBUSLCK
15:12 RW-L 0h
Debug Event Set Lane Select 3
Note: Locked by DBGBUSLCK
11:8 RW-L 0h
Debug Event Set Lane Select 2
Note: Locked by DBGBUSLCK
7:4 RW-L 0h
Debug Event Set Lane Select 1
Note: Locked by DBGBUSLCK
3:0 RW-L 0h
Debug Event Set Lane Select 0
Note: Locked by DBGBUSLCK
IRP1DELS
Bus: 0 Device: 5 Function: 0 Offset: 810
Bit Attr
Reset
Value
Description
63:36 RV 0h Reserved
35:32 RW-L 0h
Debug Event Set Lane Select 8
Note: Locked by DBGBUSLCK
31:28 RW-L 0h
Debug Event Set Lane Select 7
Note: Locked by DBGBUSLCK
27:24 RW-L 0h
Debug Event Set Lane Select 6
Note: Locked by DBGBUSLCK
23:20 RW-L 0h
Debug Event Set Lane Select 5
Note: Locked by DBGBUSLCK
19:16 RW-L 0h
Debug Event Set Lane Select 4
Note: Locked by DBGBUSLCK
15:12 RW-L 0h
Debug Event Set Lane Select 3
Note: Locked by DBGBUSLCK
11:8 RW-L 0h
Debug Event Set Lane Select 2
Note: Locked by DBGBUSLCK
7:4 RW-L 0h
Debug Event Set Lane Select 1
Note: Locked by DBGBUSLCK
3:0 RW-L 0h
Debug Event Set Lane Select 0
Note: Locked by DBGBUSLCK