Datasheet

Datasheet, Volume 2 183
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Processor Integrated I/O (IIO) Configuration Registers
3.3.3.36 IRP_MISC_DFX1—Coherent Interface Miscellaneous 
DFx 1 Register
13:9 RW-L 09h
Minimum Free Conflict Queue Entries
The number of free conflict entries at which the non-isoc transactions are
throttled. There are a total of 32 entries to begin with.
Note: Locked by DBGBUSLCK
8RW-L 1b
Check IO Config Format
Does some format checking (address alignment) for io and cfg transactions.
Note: Locked by DBGBUSLCK
7RW-L 1b
Check LT Read Format
Does some format checking for lt transactions.
Note: Locked by DBGBUSLCK
6RW-L 1b
Use Isoch Overflow Queue
Use a different queue between switch and IRP for isoc transaction.
Note: Locked by DBGBUSLCK
5RW-L 1b
Enable spl Isoch Intel VT Requests
Issue an isoc Intel VT transaction irrespective of whether another trans to the
same address is pending or not.
Note: Locked by DBGBUSLCK
4:1 RW-L 4h
Minimum Free Isoch HQ Entry
Note: Locked by DBGBUSLCK
0RV0hReserved
IRP_MISC_DFX1
Bus: 0 Device: 5 Function: 0 Offset: 804
Bit Attr
Reset
Value
Description
31:14 RV 0h Reserved
13 RW-L 0b Use BGF Credit for BGF Empty
12 RV 0h Reserved
11:10 RW-L 00b
Config Retry Timeout
0h = 32 us
1h = 256 ms
2h = 4 sec
3h = 64 sec
Has a +100% timeout error
Note: Locked by DBGBUSLCK
9:8 RW-L 00b
Debug Field Select
Note: Locked by DBGBUSLCK
7:2 RW-L 0h
Debug Entry Number Select
Note: Locked by DBGBUSLCK
1RW-L 1b
Auto Debug Signal Enable
puts out cache entry related info on a round robin basis
Note: Locked by DBGBUSLCK
0RW-L 0b
Debug Signal Enable
Enables reading address CAM in unused cycles.
Note: Locked by DBGBUSLCK
IRP_MISC_DFX0
Bus: 0 Device: 5 Function: 0 Offset: 800
Bit Attr
Reset
Value
Description