Datasheet
Processor Integrated I/O (IIO) Configuration Registers
182 Datasheet, Volume 2
3.3.3.35 IRP_MISC_DFX0—Coherent Interface Miscellaneous
DFx 0 Register
IRP_MISC_DFX0
Bus: 0 Device: 5 Function: 0 Offset: 800
Bit Attr
Reset
Value
Description
31 RW-L 0b
Disable Prefetch Ack Bypass Path
A bypass path for the pf_ack reduces latency by 3 cycles. This bit disables the
bypass.
Note: Locked by DBGBUSLCK
30 RW-L 0b
Enable Parity Error Checking
Enables Parity Error Checking in the IRP on the data received from the IIO switch
Note: Locked by DBGBUSLCK
29 RW-L 0b
Force No-Snoop on VC1 and VCm
This bit forces no snp on vc1 vcm transactions. This bit needs to be used in
conjunction with fast path disable for vc1 vcm transactions. otherwise switch will
receive an additional prh_done
Note: Locked by DBGBUSLCK
28 RW-L 1b
Dump Prefetch with Conflicts
This bit is a performance optimization. If there is a wr pf that is followed by a
conflicting transaction, this just sends a fake pf_ack without sending it to CBO
Note: Locked by DBGBUSLCK
27 RW-L 1b
Use Latest Read Prefetch
This bit is a performance optimization. if a rd pf 1, rd pf 2, rd f 1, rd f 2 is sent,
then the data from rd pf 2 is used for rd f 1. This is ok since the data being sent is
an even later version than what is ok.
Note: Locked by DBGBUSLCK
26 RW-L 0b
Disregard SNUM while merging
This bit merges non back to back writes. This might cause deadlock. It needs to
be used with flush transactions on timeout knob.
Note: Locked by DBGBUSLCK
25 RW-L 0b
Disregard Posted Ordering
Writes are sent in any random order. This might cause deadlock. It needs to be
used with aging timer rollover.
Note: Locked by DBGBUSLCK
24 RW-L 1b
Disregard Intel VT-d Reuse Hint
This bit disregards the reuse hint from Intel VT-d. Results are in a fetch to CBO
every time.
Note: Locked by DBGBUSLCK
23:22 RW-L 00b
Ageing Timer Rollover
0h = Disabled
1h = 32 us
2h = 128 us
3h = 512 us
There is an error of abt +100%. The numbers maybe moved around a little to
facilitate pre-si validation
Note: Locked by DBGBUSLCK
21:15 RW-L 03h
Threshold to flush reusable lines
The number of free lines left before some of the older Intel VT-d reuse lines are
flushed
Note: Locked by DBGBUSLCK
14 RW-L 0b
Repeat Dumped Prefetch
This bit is a performance optimization. if ownership is lost due to a tickle, it is
reissued independent of the switch coming back without a fetch from switch.
Note: Locked by DBGBUSLCK