Datasheet

Processor Integrated I/O (IIO) Configuration Registers
180 Datasheet, Volume 2
24 RW 0b
Disable all allocating flows
When this bit is set, IIO will no more issue any new inbound IDI command that
can allocate into LLC. Instead, all the writes will use one of the non-allocating
commands – PCIWiL/PCIWiLF/PCINSWr/PCINSWrF. This is provided primarily for
PSMI where a mode is needed to not allocate into the LLC. Software should set
this bit only when no requests are being actively issued on IDI. So either a lock/
quiesce flow should be employed before this bit is set/cleared or it should be set
up before DMA is enabled in system.
23 RV 0h Reserved
22 RW 0b Disable RO on writes from CB DMA
21 RW 0b
Disable DCA from CB DMA
1 = DCA is disabled from CB DMA engine and the write are treated as normal
non-DCA writes
20 RW 0b
Switch Arbitration Weight for CB DMA
1 = CB DMA arbitration weight is treated equivalent to a x16 PCIe port.
0 = It is equivalent to a x8 PCie port.
19 RW 0b
RVGAEN
Remote VGA Enable Enables VGA accesses to be sent to remote node.
1 = Accesses to the VGA region (A_0000h to B_FFFFh) will be forwarded to the
CBo where it will determine the node ID where the VGA region resides. It will
then be forwarded to the given remote node.
0 = VGA accesses will be forwarded to the local PCIe port that has its VGAEN set.
If none have their VGAEN set, then the request will be forwarded to the local
DMI port, if operating in DMI mode. If it is not operating in DMI mode, then
the request will be aborted.
18 RW 1b
Disable inbound RO for VC0/VCp writes
When enabled, this mode will treat all inbound write traffic as RO=0 for VC0. This
affects all PCI Express ports and the DMI port.
0 = Ordering of inbound transactions is based on RO bit for VC0
1 = RO bit is treated as ’0’ for all inbound VC0 traffic
This impacts only the NS write traffic because for snooped traffic RO bit is ignored
by hardware. When this bit is set, the NS write (if enabled) BW is going to be
generally bad.
This bit does not impact VC1 and VCm writes.
17:16 RW 01b
VC1 Write Ordering
This mode is used to control VC1 write traffic from DMI (Intel High Definition
Audio).
00 = Reserved
01 = Serialize writes on CSI issuing one at a time
10 = Pipeline writes on CSI except for writes with Tag value of 21h which are
issued only after prior writes have all completed and reached global
observability
11 = Pipeline writes on CSI based on RO bit. That is, if RO=1, pipeline a write on
Intel QPI without waiting for prior write to have reached global observability.
If RO=0, then it needs to wait till prior writes have all reached global
observability.
15 RW 0b
DMI VC1 Intel VT-d fetch Ordering
This mode is to allow VC1 Intel VT-d conflicts with outstanding VC0 Intel VT-d
reads on IDI to be pipelined. This can occur when Intel VT-d tables are shared
between Intel High Definition Audio (VC1) and other devices. To ensure QoS the
Intel VT-d reads from VC1 need to be issued in parallel with non-Isoc accesses to
the same cacheline.
0 = Serialize all IDI address conflicts to DRAM
1 = Pipeline Intel VT-d reads from VC1 with address conflict on IDI
Note: A maximum of 1 VC1 Intel VT-d read and 1 non-VC1 Intel VT-d read to the
same address can be outstanding on IDI.
IIOMISCCTRL
Bus: 0 Device: 5 Function: 0 Offset: 1C0
Bit Attr
Reset
Value
Description