Datasheet

18 Datasheet, Volume 2
4.4.2.20 PRIP_TURBO_PWR_LIM—Primary Plane Turbo Power 
Limitation Register ..................................................................486
4.4.2.21 PRIMARY_PLANE_CURRENT_CONFIG_CONTROL—Primary 
Plane Current Configuration Control Register...............................487
4.4.3 PCU1 Registers.....................................................................................488
4.4.3.1 SSKPD—Sticky Scratchpad Data Register....................................488
4.4.3.2 C2C3TT—C2 to C3 Transition Timer Register...............................488
4.4.3.3 PCIE_ILTR_OVRD—PCI Express* Latency Tolerance 
Requirement (LTR) Override Register.........................................489
4.4.3.4 BIOS_MAILBOX_DATA—BIOS Mailbox Data Register ....................490
4.4.3.5 BIOS_MAILBOX_INTERFACE—BIOS Mailbox Interface Register ......490
4.4.3.6 BIOS_RESET_CPL—BIOS Reset Complete Register.......................491
4.4.3.7 MC_BIOS_REQ—MC_BIOS_REQ Register....................................493
4.4.3.8 CSR_DESIRED_CORES—Desired Cores Register...........................493
4.4.3.9 SAPMCTL—System Agent Power Management Control Register......494
4.4.3.10 M_COMP—Memory COMP Control Register..................................496
4.4.3.11 SAPMTIMERS—System Agent Power Management Timers Register.496
4.4.3.12 RINGTIMERS—RING Timers Register..........................................497
4.4.3.13 BANDTIMERS—PLL Self Banding Timers Register .........................497
4.4.4 PCU2 Registers.....................................................................................498
4.4.4.1 CPU_BUS_NUMBER—CPU Bus Number Register...........................498
4.4.4.2 SA_TEMPERATURE—SA Temperature Register.............................498
4.4.4.3 DYNAMIC_PERF_POWER_CTL Register .......................................498
4.4.4.4 GLOBAL_PKG_C_S_CONTROL Register.......................................499
4.4.4.5 GLOBAL_NID_MAP_REGISTER_0 Register...................................500
4.4.4.6 PKG_CST_ENTRY_CRITERIA_MASK Register ...............................501
4.4.4.7 PRIMARY_PLANE_RAPL_PERF_STATUS Register...........................501
4.4.4.8 PACKAGE_RAPL_PERF_STATUS Register.....................................502
4.4.4.9 DRAM_POWER_INFO Register ...................................................502
4.4.4.10 DRAM_ENERGY_STATUS Register..............................................503
4.4.4.11 DRAM_ENERGY_STATUS_CH[0:3]—DRAM Energy Status 
CH0 Register ..........................................................................503
4.4.4.12 DRAM_PLANE_POWER_LIMIT—DRAM Plane Power Limit Register ...504
4.4.4.13 DRAM_RAPL_PERF_STATUS—DRAM RAPL Perf Status Register.......504
4.4.4.14 PERF_P_LIMIT_CONTROL Register.............................................505
4.4.4.15 IO_BANDWIDTH_P_LIMIT_CONTROL Register.............................506
4.4.4.16 MCA_ERR_SRC_LOG—MCA Error Source Log Register ..................507
4.4.4.17 SAPMTIMERS3—System Agent Power Management Timers3 
Register.................................................................................507
4.4.4.18 THERMTRIP_CONFIG—ThermTrip Configuration Register...............508
4.4.4.19 PERFMON_PCODE_FILTER—Perfmon Pcode Filter Register.............508
4.4.5 PCU3 Registers.....................................................................................509
4.4.5.1 DEVHIDE[0:7]—Function 0 Device Hide Register .........................509
4.4.5.2 CAP_HDR Register...................................................................509
4.4.5.3 CAPID0 Register......................................................................510
4.4.5.4 CAPID1 Register......................................................................511
4.4.5.5 CAPID2 Register......................................................................513
4.4.5.6 CAPID3 Register......................................................................514
4.4.5.7 CAPID4 Register......................................................................515
4.4.5.8 FLEX_RATIO—Flexible Ratio Register..........................................516
4.4.5.9 RESOLVED_CORES_MASK—Resolved Cores Mask Register............516
4.4.5.10 PWR_LIMIT_MISC_INFO Register ..............................................516
4.5 Processor Utility Box (UBOX) Registers ...............................................................517
4.5.1 CSR Group...........................................................................................517
4.5.2 Processor Utility Box (UBOX) Registers ....................................................519
4.5.2.1 CPUNODEID—Node ID Configuration Register .............................519
4.5.2.2 CPUEnable—CPU Enable Register...............................................519
4.5.2.3 IntControl—Interrupt Control Register........................................520
4.5.2.4 LockControl—Lock Control Register............................................521
4.5.2.5 GIDNIDMAP—Node ID Mapping Register.....................................521
4.5.2.6 CoreCount—Number of Cores Register .......................................522