Datasheet

Datasheet, Volume 2 175
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Processor Integrated I/O (IIO) Configuration Registers
3.3.3.28 VTGENCTRL2—Intel
®
VT-d General Control 2 Register
VTGENCTRL2
Bus: 0 Device: 5 Function: 0 Offset: 18C
Bit Attr
Reset
Value
Description
31:12 RV 0h Reserved
11 RW-L 0b
LRU Count Control
This bit controls what increments the LRU counter that is used to degrade the LRU
bits in the IOTLB, L1/L2, and L3 caches.
1 = Count Cycles (same as TB)
0 = Count Requests
10:7 RW-LB 7h
LRU Timer
This bit controls the rate at which the LRU buckets should degrade.
If in "Request" mode (LRUCTRL = 0), then LRU will be degraded after 16 * N
requests where N is the value of this field.
If we are in "Cycles" mode (CRUCTRL = 1), then LRU will be degraded after 256 *
N cycles where N is the value of this field.
The default value of 7h (along with LRUCTRL=0) will provide a default behavior of
decreasing the LRU buckets every 112 requests.
6:5 RW-LB 01b
Prefetch Control
Queued invalidation, interrupt table read, context table reads and root table reads
NEVER have prefetch/snarf/reuse capability. This is a general rule. Beyond that
the Prefetch Control bits control additional behavior as shown below.
00 = Prefetch/snarf/reuse is turned off, that is, IRP cluster never reuses the Intel
VT-d read data
01 = Prefetch/snarf/reuse is enabled for all leaf/non-leaf Intel VT-d page walk
reads.
10 = Prefetch/snarf/reuse is enabled only on leaf (not non-leaf) Intel VT-d page
walks reads with CC.ALH bit set
11 = Prefetch/snarf/reuse is enabled on ALL leaf (not non-leaf) Intel VT-d page
walks reads regardless of the setting of the CC.ALH bit
4RV0hReserved
3RW-LB 0b
Do Not use U bit in leaf entry for leaf eviction policy on untranslated DMA
requests (AT=00b)
2RW-LB 0b
Mark non-leaf entries on translation requests with AT=01 for early
eviction
1RW-LB 0b
Do Not mark leaf entries with U=0 on translation requests with AT=01 for
early eviction
0RV0hReserved