Datasheet

Datasheet, Volume 2 173
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Processor Integrated I/O (IIO) Configuration Registers
3.3.3.25 VTBAR—Base Address Register for Intel
®
VT-d Registers
3.3.3.26 VTGENCTRL—Intel
®
VT-d General Control Register
VTBAR
Bus: 0 Device: 5 Function: 0 Offset: 180
Bit Attr
Reset
Value
Description
31:13 RW-LB 00000h
Intel VT-d Base Address
This field provides an aligned 8K base address for IIO registers relating to Intel
VT-d. All inbound accesses to this region are completer aborted by the IIO.
12:1 RV 0h Reserved
0RW-LB 0b
Intel VT-d Base Address Enable
Accesses to registers pointed to by VTBAR are accessible using message channel
or JTAG mini-port, irrespective of the setting of this enable bit. That is, even if this
bit is clear, read/write to Intel VT-d registers are completed normally (writes
update registers and reads return the value of the register) for accesses from
message channel or JTAG mini-port.
This bit is RW-LB (that is, lock is determined based on the ’trusted’ bit in message
channel) when VTGENCTRL[15] is set, else it is RO.
VTGENCTRL
Bus: 0 Device: 5 Function: 0 Offset: 184
Bit Attr
Reset
Value
Description
15 RW-O 0b
Lock Intel VT-d
When this bit is 0, the VTBAR[0]is RW-LB else it is RO.
14:8 RV 0h Reserved
7:4 RW-LB 0011b
Isoch/Non-Isoch HPA_LIMIT
Represents the host processor addressing limit
0000 = 2^36 (that is, bits 35:0)
0001 = 2^37 (that is, bits 36:0)
...
1010 = 2^46 (that is, bits 45:0)
When Intel VT-d translation is enabled on an Intel VT-d engine (isoch or non-
isoch), all host addresses (during page walks) that go beyond the limit specified in
this register will be aborted by IIO. Pass-through and ’translated’ ATS accesses
carry the host-address directly in the access and are subject to this check as well.
3:0 RW-LB 8h
Isoch/Non-Isoch GPA_LIMIT
Represents the guest virtual addressing limit for the non-Isoch Intel VT-d engine.
0000 = 2^40 (That is, bits 39:0)
0001 = 2^41 (That is, bits 40:0)
..
0111 = 2^47
1000 = 2^48
Others = Reserved
When Intel VT-d translation is enabled, all incoming guest addresses from PCI
Express, associated with the non-isoch Intel VT-d engine, that go beyond the limit
specified in this register will be aborted by IIO and a UR response returned. This
register is not used when translation is not enabled. Note that ’translated’ and
’pass-through’ addresses are in the ’host-addressing’ domain and NOT ’guest-
addressing’ domain and hence GPA_LIMIT checking on those accesses are
bypassed and instead HPA_LIMIT checking applies.