Datasheet

Processor Integrated I/O (IIO) Configuration Registers
172 Datasheet, Volume 2
3.3.3.24 CIPINTRS—Coherent interface Protocol Interrupt Status Register
This register is to be polled by BIOS to determine if internal pending system interrupts
are drained out of IIO.
11 RW 1b INTR Mask
10 RW 1b SMI Mask
9RW1bInit Mask
8RW1bNMI Mask
7RW-L 0b
IA32 or IPF
Note: Locked by RSPLCK
6:2 RV 0h Reserved
1RW0bInterrupt Logical Mode
0RW-L 0b
Cluster Check Sampling Mode
Note: Locked by RSPLCK
CIPINTRC
Bus: 0 Device: 5 Function: 0 Offset: 14C
Bit Attr
Reset
Value
Description
CIPINTRS
Bus: 0 Device: 5 Function: 0 Offset: 154
Bit Attr
Reset
Value
Description
31 RW1CS 0b
Externally generated VLWSignaled
This is set when IIO forwards a VLW from PCH that had the SMI bit asserted.
30 RW1CS 0b
Externally generated VLWSignaled
This is set when IIO forwards a VLW from PCH that had the NMI bit asserted.
29:8 RV 0h Reserved
7RO-V0bMCA RAS Event Pending
6RO-V0bNMI RAS Event Pending
5RO-V0bSMI RAS Event Pending
4RO-V0bINTR Event Pending
3RO-V0bA20M Event Pending
2RO-V0bINIT Event Pending
1RO-V0bNMI Event Pending
0RO-V0b
VLW message pending
(either generated internally or externally)